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vct 38xxa/b video/controller/teletext ic family edition jan. 8, 2002 6251-518-1pd preliminar y d a t a sheet micr onas micronas
vct 38xxa/b preliminary data sheet 2 micronas contents page section title 7 1. introduction 81.1.features 8 1.1.1. video features 8 1.1.2. microcontroller features 8 1.1.3. osd features 8 1.1.4. teletext features 8 1.1.5. audio features 8 1.1.6. general features 9 1.2. chip architecture 10 1.3. system application 11 2. video processing 11 2.1. introduction 11 2.2. video front-end 11 2.2.1. input selector 11 2.2.2. clamping 11 2.2.3. automatic gain control 11 2.2.4. analog-to-digital converters 12 2.2.5. digitally controlled clock oscillator 12 2.2.6. analog video output 12 2.3. adaptive comb filter 13 2.4. color decoder 13 2.4.1. if-compensation 14 2.4.2. demodulator 14 2.4.3. chrominance filter 14 2.4.4. burst detection / saturation control 14 2.4.5. color killer operation 15 2.4.6. automatic standard recognition 15 2.4.7. pal compensation/1-h comb filter 16 2.4.8. luminance notch filter 16 2.4.9. skew filtering 16 2.5. horizontal scaler 17 2.6. black-line detector 17 2.7. test pattern generator 17 2.8. video sync processing 18 2.9. display processing 18 2.9.1. luma contrast adjustment 18 2.9.2. black-level expander 19 2.9.3. dynamic peaking 20 2.9.4. digital brightness adjustment 20 2.9.5. soft limiter 20 2.9.6. chroma interpolation 20 2.9.7. chroma transient improvement 21 2.9.8. inverse matrix 21 2.9.9. rgb processing 21 2.9.10. osd color look-up table 21 2.9.11. picture frame generator 22 2.9.12. priority decoder 22 2.9.13. scan velocity modulation 22 2.9.14. display phase shifter 24 2.10. video back-end 24 2.10.1. crt measurement and control 25 2.10.2. scart output signal 26 2.10.3. average beam current limiter 26 2.10.4. analog rgb insertion 26 2.10.5. fast-blank monitor
contents, continued page section title preliminary data sheet vct 38xxa/b micronas 3 28 2.11. synchronization and deflection 28 2.11.1. deflection processing 28 2.11.2. angle and bow correction 28 2.11.3. horizontal phase adjustment 29 2.11.4. vertical and east/west deflection 29 2.11.5. eht compensation 30 2.11.6. protection circuitry 30 2.12. reset function 30 2.13. standby and power-on 31 2.14. i 2 c bus slave interface 31 2.14.1. control and status registers 44 2.14.1.1. scaler adjustment 46 2.14.1.2. calculation of vertical and east-west deflection coefficients 48 3. text and osd processing 48 3.1. introduction 48 3.2. sram interface 48 3.3. text controller 50 3.4. teletext acquisition 50 3.5. teletext page management 50 3.5.1. memory manager 51 3.5.2. memory organization 51 3.5.3. page table 53 3.5.4. ghost row organization 54 3.5.5. subpage manager 55 3.6. wst display controller 56 3.7. display memory 58 3.8. character generator 59 3.8.1. character code mapping 60 3.8.2. character font rom 61 3.8.3. latin font mapping 62 3.8.4. cyrillic font mapping 63 3.8.5. arabic font mapping 64 3.8.6. closed caption font (on vct 38xxb only!) 65 3.8.7. character font structure 66 3.9. national character mapping 68 3.10. four-color mode 69 3.11. osd layer 70 3.12. command language 78 3.13. i/o register 85 3.14. i 2 c-bus slave interface 85 3.14.1. subaddressing 86 3.14.1.1. cpu subaddressing 86 3.14.1.2. dram subaddressing 86 3.14.1.3. command subaddressing 87 3.14.1.4. data subaddressing 87 3.14.1.5. hardware identification
vct 38xxa/b preliminary data sheet 4 micronas contents, continued page section title 88 4. audio processing 88 4.1. introduction 88 4.2. input select 88 4.3. volume control 88 4.4. i 2 c-bus slave interface 89 5. tv controller 89 5.1. introduction 89 5.2. cpu 89 5.2.1. cpu slow mode 90 5.3. ram and rom 90 5.3.1. address map 90 5.3.2. bootloader 91 5.4. control register 93 5.5. standby registers 94 5.6. test registers 95 5.7. reset logic 95 5.7.1. alarm function 95 5.7.2. software reset 95 5.7.2.1. from standby into normal mode 95 5.7.2.2. from normal into standby mode 96 5.7.3. internal reset sources 96 5.7.3.1. supply supervision 96 5.7.3.2. clock supervision 97 5.7.3.3. watchdog 98 5.7.4. external reset sources 98 5.7.5. summary of module reset states 98 5.7.6. reset registers 99 5.8. memory banking 99 5.8.1. banking register 101 5.9. dma interface 103 5.9.1. dma registers 104 5.10. interrupt controller 104 5.10.1. features 104 5.10.2. general 104 5.10.3. initialization 104 5.10.4. operation 104 5.10.5. inactivation 106 5.10.6. precautions 107 5.10.7. interrupt registers 109 5.10.8. interrupt assignment 109 5.10.8.1. interrupt multiplexer 111 5.10.9. port interrupt module 113 5.10.10. interrupt timing 114 5.11. memory patch module 114 5.11.1. features 114 5.11.2. general 114 5.11.3. initialization 115 5.11.4. patch operation 115 5.11.5. patch registers 116 5.12. i 2 c-bus master interface 118 5.12.1. i 2 c bus master interface registers 120 5.13. timer t0 and t1 120 5.13.1. features 120 5.13.2. operation 121 5.13.3. timer registers
contents, continued page section title preliminary data sheet vct 38xxa/b micronas 5 122 5.14. capture compare module (capcom) 122 5.14.1. features 123 5.14.2. initialization 123 5.14.3. operation of ccc 123 5.14.3.1. operation of subunit 123 5.14.3.2. compare and output action 124 5.14.3.3. capture and input action 124 5.14.3.4. interrupts 124 5.14.4. inactivation 125 5.14.5. capcom registers 127 5.15. pulse width modulator 127 5.15.1. features 127 5.15.2. general 127 5.15.3. initialization 127 5.15.4. operation 127 5.15.5. pwm registers 128 5.16. tuning voltage pulse width modulator 128 5.16.1. features 128 5.16.2. general 129 5.16.3. initialization 129 5.16.4. operation 129 5.16.5. tvpwm registers 130 5.17. a/d converter (adc) 130 5.17.1. features 131 5.17.2. operation 131 5.17.3. measurement errors 131 5.17.4. comparator 132 5.17.5. adc registers 133 5.18. closed caption module (cc) 133 5.18.1. features 134 5.18.2. operation 134 5.18.2.1. lowpass filter 134 5.18.2.2. input timing 134 5.18.2.3. threshold adaption 134 5.18.2.4. bitslicing 134 5.18.2.5. timing recovery 134 5.18.2.6. shift register 134 5.18.2.7. controlling 134 5.18.2.8. formatter 135 5.18.3. ccm registers 137 5.19. ports 137 5.19.1. port assignment 138 5.19.2. universal ports p1 to p3 138 5.19.2.1. features 139 5.19.2.2. universal port mode 139 5.19.3. universal port registers 140 5.19.4. i 2 c ports p40 and p41 140 5.19.4.1. features 141 5.19.5. audio ports p42 to p46 141 5.19.5.1. features 142 5.19.6. clk20 output port 142 5.19.6.1. features 143 5.20. i/o register cross reference
vct 38xxa/b preliminary data sheet 6 micronas contents, continued page section title 147 6. specifications 147 6.1. outline dimensions 148 6.2. pin connections and short descriptions 152 6.3. pin descriptions for psdip64 package 154 6.4. pin descriptions for pmqfp128 package 155 6.5. pin configuration 157 6.6. pin circuits 160 6.7. electrical characteristics 160 6.7.1. absolute maximum ratings 160 6.7.2. recommended operating conditions 160 6.7.2.1. general recommendations 161 6.7.2.2. analog input and output recommendations 162 6.7.2.3. recommended crystal characteristics 163 6.7.3. characteristics 163 6.7.3.1. general characteristics 163 6.7.3.2. test input 164 6.7.3.3. reset input/output 164 6.7.3.4. i 2 c bus interface 165 6.7.3.5. 20-mhz clock output 165 6.7.3.6. analog video output 165 6.7.3.7. a/d converter reference 166 6.7.3.8. analog video front-end and a/d converters 168 6.7.3.9. analog rgb and fb inputs 169 6.7.3.10. horizontal flyback input 169 6.7.3.11. horizontal drive output 169 6.7.3.12. vertical safety input 169 6.7.3.13. vertical protection input 170 6.7.3.14. vertical and east/west d/a converter output 170 6.7.3.15. interlace output 170 6.7.3.16. sense a/d converter input 170 6.7.3.17. range switch output 171 6.7.3.18. d/a converter reference 171 6.7.3.19. analog rgb outputs, d/a converters 174 6.7.3.20. scan velocity modulation output 174 6.7.3.21. analog audio inputs and outputs 175 6.7.3.22. adc input port 175 6.7.3.23. universal port & memory interface 176 6.7.3.24. memory interface 177 7. application 180 8. glossary of abbreviations 180 9. references 182 10. data sheet history
preliminary data sheet vct 38xxa/b micronas 7 video/controller/teletext ic family release note: this data sheet describes functions and characteristics of the vct 38xxa-c4 and vct 38xxb-d6. 1. introduction the vct 38xxa/b is an ic family of high-quality single- chip tv processors. modular design and a submicron technology allow the economic integration of features in all classes of tv sets. the vct 38xxa/b family is based on functional blocks contained and approved in existing products like vdp 3120b, tpu 3050s, and ccz 3005k. each member of the family contains the entire video, display, and deflection processing for 4:3 and 16:9 50/ 60-hz tv sets. the integrated microcontroller is sup- ported by a powerful osd generator with integrated teletext acquisition which can be upgraded with on- chip page memory. with volume control and audio input select the basic audio features for mono tv sets are integrated. an overview of the vct 38xxa/b sin- gle-chip tv processor family is given in fig. 1?1 on page 7. the vct 38xxa/b family offers a rich feature set, cov- ering the whole range of state-of-the-art 50/60-hz tv applications. in comparison to the vct 38xxa the vct 38xxb offers the following features: ? one additional composite video input ? analog luma/chroma adder for video output ? closed caption module ? additional 12k character rom fig. 1?1: vct 38xxa/b family overview adaptive comb filter panorama scaler blackline detector picture improvements (color transient improv., soft limiter, black-level expander) 10 page teletxt vct 38xxa/b family vct 3801a/b ? ?? ? ? ? ?? ? ? ??? ?? ? ? ? ?? ?? ?? ?
vct 38xxa/b preliminary data sheet 8 micronas 1.1. features 1.1.1. video features ? four composite video inputs ( vct 38xxa ) ? five composite video inputs ( vct 38xxb ) ? analog yc r c b input, two s-vhs inputs ? y/c adder for video output ( vct 38xxb only! ) ? composite video monitor ? multistandard color decoder (1 crystal) ? multistandard sync decoder ? black-line detector ? adaptive 2h comb filter y/c separator ? horizontal scaling (0.25 to 4) ? panoramavision ? black-level expander ? dynamic peaking ? soft limiter (gamma correction) ? color transient improvement ? programmable rgb matrix ? analog rgb/fastblank input ? half-contrast switch ? picture frame generator ? scan velocity modulation output ? high-performance h/v deflection ? angle and bow correction ? separate adc for tube measurements ? eht compensation 1.1.2. microcontroller features ? 8-bit, 10-mhz cpu (65c02) ? 96 kb program rom on chip ? 1 kb program ram on chip ? memory banking ? 16-input, 16-level interrupt controller ? patch module for 10 rom locations ? two 16-bit reloadable timers ? capture compare module ? watchdog timer ? 14-bit pwm for voltage synthesis ? four 8-bit pwms ? 10-bit adc with 15:1 input mux ? i 2 c bus master interface ? 24 programmable i/o ports ? closed caption module ( vct 38xxb only! ) 1.1.3. osd features ? 3 kb osd ram on chip ? wst level 1.5 compliant ? wst level 2 parallel attributes ? 32 foreground/background colors ? programmable color look-up table ? 1024 mask programmable characters ( vct 38xxa ) ? 2000 mask programmable characters ( vct 38xxb ) ? 24 national languages (latin, cyrillic, greek, arabic, farsi, hebrew) ? character matrix 8x8, 8x10, 8x13, 10x8, 10x10, 10x13 ? vertical soft scroll ? 4-color mode for user font 1.1.4. teletext features ? four programmable video inputs ( vct 38xxa ) ? five programmable video inputs ( vct 38xxb ) ? acquisition is independent from display part ? adaptive data slicer ? signal quality detection ? wst, pdc, vps, and wss acquisition ? high-level command language ? epg, flof, and top support ? 10 pages memory on chip ? up to 500 pages with external sram 1.1.5. audio features ? three mono inputs ? two mono outputs ? programmable channel select ? volume control for one mono channel 1.1.6. general features ? submicron cmos technology ? low-power standby mode ? single 20.25-mhz crystal ? 64-pin psdip package ? 128-pin pmqfp package ? emulator chip for software development
preliminary data sheet vct 38xxa/b micronas 9 1.2. chip architecture fig. 1 ? 2: block diagram of the vct 38xxa/b (shaded blocks are optional) the block diagram does not show the additional features of vct 38xxb. video front-end comb filter color decoder display processor video back-end panorama scaler 4 3 4 12 31 2 i 2 c master 3kb osd 96 kb cpu rom tpu dma cpu 24 io ports watchdog 2 capcom 2 timer 15:1 mux 10-bit adc 8-bit pwm audio 3 2 clock oscillator 1kb cpu ram xtal1 xtal2 vin ain pxy adb, db, cb rgbout rgbin vert prot hflb sense i 2 c xref hout vrd vrt sgnd color, prio msync i 2 c vsupab vsupp1 gndp1 reset logic resq vsups test gndab vsupaf vsupd gndaf gndd rsw 2 gndm ew 8 14-bit pwm 2 2 3 cin svm video gnds clk20 rdy be 24 kb vct 38xxa/b aout vsync vout 24 kb rom 3kb osd ram pict.improv 16 kb te x t ram
vct 38xxa/b preliminary data sheet 10 micronas 1.3. system application fig. 1 ? 3: single-chip tv with vct 38xxa/b vct 38xxa/b 20.25mhz 512k sram cvbs1 cvbs2 c r optional memory extension y c b c loudspeaker tuner/scart/frontav analog video analog audio crt analog rgb scart 512k rom/ flash ce ce oe2 we2 adb db oe1 we1 y
preliminary data sheet vct 38xxa/b micronas 11 2. video processing 2.1. introduction the vct 38xxa/b includes complete video, display, and deflection processing. in the following sections the video processing part of the vct 38xxa/b will be named vdp for short. all processing is done digitally, the video front-end and video back-end are interfacing to the analog world. most functions of the vdp can be controlled by soft- ware via i 2 c bus slave interface (see section 2.14. on page 31). 2.2. video front-end this block provides the analog interfaces to all video inputs and mainly carries out analog-to-digital conver- sion for the following digital video processing. a block diagram is given in fig. 2 ? 1. most of the functional blocks in the front-end are digi- tally controlled (clamping, agc, and clock-dco). the control loops are closed by the fast processor ( ? fp ? ) embedded in the video decoder. 2.2.1. input selector up to eight analog inputs can be connected. four inputs (five in case of vct 38xxb) are for input of com- posite video or s-vhs luma signal. these inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. two chroma inputs can be used for connection of s-vhs carrier-chrominance sig- nal. these inputs are internally biased and have a fixed gain amplifier. for analog yc r c b signals (e.g. from dvd players) one of the selected luminance inputs is used together with cbin and crin inputs. 2.2.2. clamping the composite video input signals are ac-coupled to the ic. the clamping voltage is stored on the coupling capacitors and is generated by digitally controlled cur- rent sources. the clamping level is the back porch of the video signal. s-vhs chrominance is also ac-cou- pled. the input pin is internally biased to the center of the adc input range. the chrominance inputs for yc r c b need to be ac-coupled by 220 nf clamping capacitors. it is strongly recommended to use 5-mhz anti-alias low-pass filters on each input. each channel is sampled at 10.125 mhz with a resolution of 8 bit and a clamping level of 128. 2.2.3. automatic gain control a digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/ ? 4.5 db in 64 logarithmic steps to the optimal range of the adc. the gain of the video input stage including the adc is 213 steps/v with the agc set to 0 db. the gain of the chrominance path in the yc r c b mode is fix and adapted to a nominal amplitude of 0.7 v pp . however, if an overflow of the adc occurs an extended signal range from 1 v pp can be selected. 2.2.4. analog-to-digital converters two adcs are provided to digitize the input signals. each converter runs with 20.25 mhz and has 8 bit res- olution. an integrated bandgap circuit generates the required reference voltages for the converters. fig. 2 ? 1: video front-end vin2 vin3 vin4 cin1 vin1 bias adc adc gain clamp input frequency reference generation dvco 150 ppm agc +6/ ? 4.5 db digital cvbs or luma digital chroma system clocks 20.25 mhz cvbs/y cvbs/y cvbs/y cvbs/y chroma mux cin2 chroma clamp cbin chroma crin mux vout cvbs/y 3 vin5 cvbs/y +
vct 38xxa/b preliminary data sheet 12 micronas 2.2.5. digitally controlled clock oscillator the clock generation is also a part of the analog front- end. the crystal oscillator is controlled digitally by the control processor. the clock frequency can be adjusted within 150 ppm. 2.2.6. analog video output the input signal of the luma adc is available at the analog video output pin. the signal at this pin must be buffered by a source follower. the output voltage is 2 v, thus the signal can be used to drive a 75- ? line. the magnitude is adjusted with an agc in 8 steps together with the main agc. in case of vct 38xxb it is possible to enable a y/c- adder. the analog sum of the selected luma and chroma input signals is available at the video output pin. this allows recording of s-vhs input signals via video output. 2.3. adaptive comb filter the adaptive comb filter is used for high-quality lumi- nance/chrominance separation for pal or ntsc sig- nals. the comb filter improves the luminance resolu- tion (bandwidth) and reduces interferences like cross-luminance and cross-color artifacts. the adap- tive algorithm can eliminate most of the mentioned errors without introducing new artifacts or noise. a block diagram of the comb filter is shown in fig. 2 ? 2. the filter uses two line delays to process the informa- tion of three adjacent video lines. to have a fixed phase relationship of the color subcarrier in the three channels, the system clock (20.25 mhz) is locked to the color subcarrier. this allows the processing of all color standards and substandards using a single crys- tal frequency. the cvbs signal in the three channels is filtered at the subcarrier frequency by a set of bandpass/notch fil- ters. the output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/notch filter signals.the comb filter uses the middle line as reference, therefore, the comb filter delay is one line. if the comb filter is switched off, the delay lines are used to pass the luma/ chroma sig- nals from the a/d converters to the luma/ chroma out- puts. thus, the comb filter delay is always one line. various parameters of the comb filter are adjustable, hence giving to the user the ability to adjust his own desired picture quality. two parameters (ky, kc) set the global gain of luma and chroma comb separately; these values directly weigh the adaption algorithm output. in this way, it is possible to obtain a luma/chroma separation ranging from standard notch/bandpass to full comb decoding. the parameter kb allows to choose between the two proposed comb booster modes. this so-called feature widely improves vertical high-to-low frequency transi- tions areas, the typical example being a multiburst to dc change. for kb=0, this improvement is kept mod- erate, whereas, in case of kb=1, it is maximum, but the risk to increase the ? hanging dots ? amount for some given color transitions is higher. using the default setting, the comb filter has separate luma and chroma decision algorithms; however, it is possible to switch the chroma comb factor to the cur- rent luma adaption output by setting cc to 1. fig. 2 ? 2: block diagram of the adaptive comb filter (pal mode) 1h delay line 1h delay line cvbs input chroma input bandpass filter bandpass filter bandpass/ notch filter luma / chroma mixers adaption logic luma output chroma output
preliminary data sheet vct 38xxa/b micronas 13 another interesting feature is the programmable limita- tion of the luma comb amount; proper limitation, asso- ciated to adequate luma peaking, gives rise to an enhanced 2-d resolution homogeneity. this limitation is set by the parameter clim, ranging from 0 (no limi- tation) to 31 (max. limitation). the daa parameter (1:off, 0:on) is used to disable/ enable a very efficient built-in ? rain effect ? suppressor; many comb filters show this side effect which gives some vertical correlation to a 2-d uniform random area, due to the vertical filtering. this unnatural-look- ing phenomenon is mostly visible on tuner images, since they are always corrupted by some noise; and this looks like rain. 2.4. color decoder a block diagram of the color decoder is shown in fig. 2 ? 4. the luma as well as the chroma processing, is shown here. the color decoder provides also some special modes, e.g. wide band chroma format which is intended for s-vhs wide bandwidth chroma. if the adaptive comb filter is used for luma chroma sep- aration, the color decoder uses the s-vhs mode pro- cessing. the output of the color decoder is yc r c b in a 4:2:2 format. 2.4.1. if-compensation with off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color sub- carrier is compensated. four different settings of the if-compensation are possible: ? flat (no compensation) ? 6 db/octave ? 12 db/octave ? 10 db/mhz the last setting gives a very large boost to high fre- quencies. it is provided for secam signals that are decoded using a saw filter specified originally for the pal standard. fig. 2 ? 3: frequency response of chroma if-compensation fig. 2 ? 4: color decoder colorpll/coloracc 1 h delay mux mux crossswitch notch filter luma / cvbs luma chroma mixer low-pass filter phase/freq demodulator acc chroma if compensation dc-reject
vct 38xxa/b preliminary data sheet 14 micronas 2.4.2. demodulator the subcarrier frequency in the demodulator is gener- ated by direct digital synthesis; therefore, substan- dards such as pal 3.58 or ntsc 4.43 can also be demodulated. 2.4.3. chrominance filter the demodulation is followed by a low-pass filter for the color difference signals for pal/ntsc. secam requires a modified low-pass function with bell-filter characteristic. at the output of the low-pass filter, all luma information is eliminated. the low-pass filters are calculated in time multiplex for the two color signals. three bandwidth settings (nar- row, normal, broad) are available for each standard. for pal/ntsc, a wide band chroma filter can be selected. this filter is intended for high bandwidth chroma signals, e.g. a non-standard wide bandwidth s-vhs signal. fig. 2 ? 5: frequency response of chroma filters 2.4.4. burst detection / saturation control in the pal/ntsc-system the burst is the reference for the color signal. the phase and magnitude outputs of the color demodulator are gated with the color key and used for controlling the phase-locked-loop (apc) of the demodulator and the automatic color control (acc) in pal/ntsc. the acc has a control range of +30... ? 6 db. color saturation can be selected once for all color standards. in pal/ntsc it is used as reference for the acc. in secam the necessary gains are calculated automatically. for secam decoding, the frequency of the burst is measured. thus, the current chroma carrier frequency can be identified and is used to control the secam processing. the burst measurements also control the color killer operation; they are used for automatic stan- dard detection as well. 2.4.5. color killer operation the color killer uses the burst-phase/burst-frequency measurement to identify a pal/ntsc or secam color signal. for pal/ntsc, the color is switched off (killed) as long as the color subcarrier pll is not locked. for secam, the killer is controlled by the toggle of the burst frequency. the burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. thus, color will be killed for very noisy signals. the color amplitude killer has a programmable hysteresis. pal/ntsc secam
preliminary data sheet vct 38xxa/b micronas 15 2.4.6. automatic standard recognition the burst-frequency measurement is also used for automatic standard recognition (together with the sta- tus of horizontal and vertical locking) thus allowing a completely independent search of the line and color standard of the input signal. the following standards can be distinguished: ? pal b,g,h,i ? pal m ? pal n ? pal 60 ? ntsc m ? ntsc 44 ? secam for a preselection of allowed standards, the recogni- tion can be enabled/disabled via i 2 c bus for each stan- dard separately. if at least one standard is enabled, the vct 38xxa/b regularly checks the horizontal and vertical locking of the input signal and the state of the color killer. if an error exists for several adjacent fields a new standard search is started. depending on the measured line number and burst frequency, the current standard is selected. for error handling the recognition algorithm delivers the following status information: ? search active (busy) ? search terminated, but failed ? found standard is disabled ? vertical standard invalid ? no color found 2.4.7. pal compensation/1-h comb filter the color decoder uses one fully integrated delay line. only active video is stored. the delay line application depends on the color stan- dard: ? ntsc: 1-h comb filter or color compensation ? pal: color compensation ? secam: crossover switch in the ntsc compensated mode, (fig. 2 ? 6c), the color signal is averaged for two adjacent lines. thus, cross-color distortion and chroma noise is reduced. in the ntsc comb filter mode, (fig. 2 ? 6d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-lumi- nance. the loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. fig. 2 ? 6: ntsc color decoding options fig. 2 ? 7: pal color decoding options fig. 2 ? 8: secam color decoding chroma notch filter 8 chroma process. cvbs y 1 h delay 8 cvbs chroma process. notch filter y 8 chroma process. luma y 8 c c r b c c r b c c r b notch filter 1 h delay 8 chroma process. cvbs y c c r b d) comb filter c) compensated a) conventional b) s-vhs chroma notch filter 1 h delay 8 chroma process. cvbs y 8 chroma process. luma y 8 1 h delay c c r b c c r b a) conventional b) s-vhs mux notch filter 1 h delay 8 chroma process. cvbs y c c r b
vct 38xxa/b preliminary data sheet 16 micronas 2.4.8. luminance notch filter if a composite video signal is applied, the color infor- mation is suppressed by a programmable notch filter. the position of the filter center frequency depends on the subcarrier frequency for pal/ntsc. for secam, the notch is directly controlled by the chroma carrier frequency. this considerably reduces the cross-lumi- nance. the frequency responses for all three systems are shown in fig. 2 ? 9. fig. 2 ? 9: frequency responses of the luma notch filter for pal, ntsc, secam 2.4.9. skew filtering the system clock is free-running and not locked to the tv line frequency. therefore, the adc sampling pat- tern is not orthogonal. the decoded yc r c b signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. the skew filters allow the application of a group delay to the input signals without introducing waveform or frequency response distortion. the amount of phase shift of this filter is controlled by the horizontal pll1. the accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. thus the 4:2:2 yc r c b data is in an orthogonal pixel format even in the case of nonstandard input signals such as vcr. 2.5. horizontal scaler the 4:2:2 yc r c b signal from the color decoder is pro- cessed by the horizontal scaler. the scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. nonlinear scaling, also called ? panoramavision ? , provides a geo- metrical distortion of the input picture. it is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. also, the inverse effect can be produced by the scaler. a summary of scaler modes is given in table 2 ? 1. the scaler contains a programmable decimation filter, a 1-line fifo memory, and a programmable interpola- tion filter. the scaler input filter is also used for pixel skew correction (see section 2.4.9. on page 16). the decimator/interpolator structure allows optimal use of the fifo memory. the controlling of the scaler is done by the internal fast processor. db mhz 10 02 4 68 10 0 ? 10 ? 20 ? 30 ? 40 db mhz 10 02 4 68 10 0 ? 10 ? 20 ? 30 ? 40 pal/ntsc notch filter secam notch filter table 2 ? 1: scaler modes mode scale factor description compression 4:3 16:9 0.75 linear 4:3 source displayed on a 16:9 tube, with side panels panorama 4:3 16:9 non- linear compr 4:3 source displayed on a 16:9 tube, borders distorted zoom 4:3 4:3 1.33 linear letterbox source (pal+) displayed on a 4:3 tube, vertical overscan with cropping of side panels panorama 4:3 4:3 non- linear zoom letterbox source (pal+) displayed on a 4:3 tube, vertical overscan, bor- ders distorted, no crop- ping
preliminary data sheet vct 38xxa/b micronas 17 2.6. black-line detector this function is available for versions with pan- orama scaler only! in case of a letterbox format input video, e.g. cinema- scope, pal+ etc., black areas at the upper and lower part of the picture are visible. it is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. the vct 38xxa/b supports this feature by a letterbox detector. for every field the number of black lines at the upper and lower part of the picture are measured and stored in the i 2 c-register blklin. to adjust the picture amplitude, the cpu reads this register, calcu- lates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, hori- zontal scaling coefficient etc., to the scaler and the deflection circuits. letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are pro- cessed as non-black lines. therefore, the subtitles are visible on the screen. to suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. dark video scenes with a low contrast level compared to the letterbox area are indicated by the blkpic bit. 2.7. test pattern generator the yc r c b outputs can be switched to a test mode where yc r c b data are generated digitally in the vct 38xxa/b. test patterns include luma/chroma ramps and flat fields. 2.8. video sync processing fig. 2 ? 10 shows a block diagram of the front-end sync processing. to extract the sync information from the video signal, a linear phase low-pass filter eliminates all noise and video contents above 1 mhz. the sync is separated by a slicer; the sync phase is measured. a variable window can be selected to improve the noise immunity of the slicer. the phase comparator mea- sures the falling edge of sync, as well as the integrated sync pulse. the sync phase error is filtered by a phase-locked loop that is computed by the fp. all timing in the front-end is derived from a counter that is part of this pll, and it thus counts synchronously to the video signal. a separate hardware block measures the signal back porch and also allows gathering the maximum/mini- mum of the video signal. this information is processed by the fp and used for gain control and clamping. for vertical sync separation, the sliced video signal is integrated. the fp uses the integrator value to derive vertical sync and field information. the information extracted by the video sync process- ing is multiplexed onto the hardware front sync signal (fsy) and is distributed to the rest of the video pro- cessing system. the data for the vertical deflection, the sawtooth, and the east-west correction signal is calculated by the vct 38xxa/b. the data is buffered in a fifo and transferred to the back-end by a single wire interface. frequency and phase characteristics of the analog video signal are derived from pll1. the results are fed to the scaler unit for data interpolation and orthogonal- ization and to the clock synthesizer for line-locked clock generation. horizontal and vertical syncs are latched with the line-locked clock. fig. 2 ? 10: sync separation block diagram phase comparator & lowpass counter front-end timing front sync lowpass 1mhz & sync slicer horizontal sync separation vertical sync separation fifo sawtooth video input skew front sync generator vertical serial data vertical sawtooth e/w parabola calculation clamping, colorkey, fifo_write pll1 clamp & signal meas. vblank field clock synthesizer syncs clock h/v syncs
vct 38xxa/b preliminary data sheet 18 micronas 2.9. display processing in the display processing the conversion from digital yc r c b to analog rgb is carried out. a block diagram is shown in fig. 2 ? 18 on page 23. in the luminance processing path, contrast and brightness adjustments and a variety of features, such as black-level expan- sion, dynamic peaking and soft limiting, are provided. in the chrominance path, the c r c b signals are con- verted to 4:4:4 format and filtered by a color transient improvement circuit. the yc r c b signals are converted by a programmable matrix to rgb color space. the display processor provides separate control set- tings for two pictures, i.e. different coefficients for a ? main ? and a ? side ? picture. the digital osd insertion circuit allows the insertion of a 5-bit osd signal. the color space for this signal is controlled by a partially programmable color look-up table (clut) and contrast adjustment. the osd signals and the display clock are synchro- nized to the horizontal flyback. for the display clock, a gate delay phase shifter is used. in the analog back- end, three 10-bit digital-to-analog converters provide the analog output signals. 2.9.1. luma contrast adjustment the contrast of the luminance signal can be adjusted by multiplication with a 6-bit contrast value. the con- trast value corresponds to a gain factor from 0 to 2, where the value 32 is equivalent to a gain of 1. the contrast can be adjusted separately for main picture and side picture. 2.9.2. black-level expander the black-level expander enhances the contrast of the picture. therefore the luminance signal is modified with an adjustable, non-linear function. dark areas of the picture are changed to black, while bright areas remain unchanged. the advantage of this black-level expander is that the black expansion is performed only if it will be most noticeable to the viewer. the black-level expander works adaptively. depending on the measured amplitudes ? l min ? and ? l max ? of the low-pass-filtered luminance and an adjustable coeffi- cient btlt, a tilt point ? l t ? is established by l t = l min + btlt (l max - l min ). above this value there is no expansion, while all lumi- nance values below this point are expanded according to: l out = l in + bam (l in - l t ) a second threshold, l tr , can be programmed, above which there is no expansion. the characteristics of the black-level expander are shown in fig. 2 ? 11 and fig. 2 ? 12. fig. 2 ? 11: characteristics of the black-level expander the tilt point l t is a function of the dynamic range of the video signal. thus, the black-level expansion is only performed when the video signal has a large dynamic range. otherwise, the expansion to black is zero. this allows the correction of the characteristics of the picture tube. fig. 2 ? 12: black-level expansion a) luminance input b) luminance input and output l min btlt bam l t l tr l max l tr bthr l in l out a) b) l min l t l max l t
preliminary data sheet vct 38xxa/b micronas 19 2.9.3. dynamic peaking especially with decoded composite signals and notch filter luminance separation, as input signals, it is nec- essary to improve the luminance frequency character- istics. with transparent, high-bandwidth signals, it is sometimes desirable to soften the image. in the vct 38xxa/b, the luma response is improved by ? dynamic ? peaking. the algorithm has been optimized regarding step and frequency response. it adapts to the amplitude of the high-frequency part. small ac amplitudes are processed, while large ac amplitudes stay nearly unmodified. the dynamic range can be adjusted from ? 14 to + 14 db for small high-frequency signals. there is sep- arate adjustment for signal overshoot and for signal undershoot. for large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. the peaking can be switched over to ? softening ? by inverting the peaking term by software. the center frequency of the peaking filter is switchable from 2.5 mhz to 3.2 mhz. for s-vhs and for notch filter color decoding, the total system frequency responses for both pal and ntsc are shown in fig. 2 ? 14. transients, produced by the dynamic peaking when switching video source signals, can be suppressed via the priority bus. fig. 2 ? 13: dynamic peaking frequency response fig. 2 ? 14: total frequency response for peaking filter and s-vhs, pal, ntsc db mhz 20 5 ? 5 ? 10 ? 15 ? 20 02 4 68 10 15 10 0 db mhz 20 5 -5 -10 -15 -20 02 4 68 10 15 10 0 db mhz 20 5 -5 -10 -15 -20 02 4 68 10 15 10 0 db mhz 20 5 -5 -10 -15 -20 02 4 68 10 15 10 0 db mhz 20 5 -5 -10 -15 -20 02 4 68 10 15 10 0 db mhz 20 5 -5 -10 -15 -20 02 4 68 10 15 10 0 db mhz 20 5 -5 -10 -15 -20 02 4 68 10 15 10 0 cf=2.5 mhz cf=2.5 mhz cf=2.5 mhz cf=3.2 mhz cf=3.2 mhz cf=3.2 mhz ntsc pal/secam s-vhs
vct 38xxa/b preliminary data sheet 20 micronas 2.9.4. digital brightness adjustment the dc-level of the luminance signal can be adjusted by adding an 8-bit number in the luminance signal path in front of the softlimiter. with a contrast adjustment of 32 (gain + 1) the signal can be shifted by 100%. after the brightness addition, the negative going signals are limited to zero. it is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut. the digital brightness adjustment works separately for main and side picture. 2.9.5. soft limiter the dynamic range of the processed luma signal must be limited to prevent the crt from overload. an appro- priate headroom for contrast, peaking and brightness can be adjusted by the tv manufacturer according to the crt characteristics. all signals above this limit will be ? soft ? -clipped. a characteristic diagram of the soft limiter is shown in fig. 2 ? 15. the total limiter consists of three parts: part 1 includes adjustable tilt point and gain. the gain before the tilt value is 1. above the tilt value, a part (0...15/16) of the input signal is subtracted from the input signal itself. therefore, the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. the tilt value can be adjusted from 0 to 511. part 2 has the same characteristics as part 1. the sub- tracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope 1 and slope 2 is greater than 16 and the input signal is above the both tilt values (see characteris- tics). finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511. 2.9.6. chroma interpolation a linear phase interpolator is used to convert the chroma sampling rate from 10.125 mhz (4:2:2) to 20.25 mhz (4:4:4). all further processing is carried out at the full sampling rate. 2.9.7. chroma transient improvement the intention of this block is to enhance the chroma resolution. a correction signal is calculated by differen- tiation of the color difference signals. the differentia- tion can be selected according to the signal bandwidth, e.g. for pal/ntsc/secam or digital component sig- nals, respectively. the amplitude of the correction sig- nal is adjustable. small noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. to elimi- nate ? wrong colors ? , which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automati- cally. fig. 2 ? 15: characteristic of soft limiter a and b and hard limiter 0 100 200 300 400 500 600 700 800 900 1023 calculation example for the softlimiter input amplitude. (the real signal processing in the limiter is 2 bit more than described here) y input 16...235 (itur) black level 16 (constant) contrast 63 dig. brightness 20 ble off peaking off limiter input signal: (yin-black level) ? contr./32 + brightn. (235-16) ? 63/32 + 20 = 451 0 2 4 6 8 10 12 14 slope 2 [0...15] 0 2 4 6 8 10 12 14 hard limiter range= 256...511 slope 1 [0...15] tilt 1 [ 0...511] tilt 2 [ 0...511] 100 200 300 400 511 output 0 part 1 part 2 limiter input
preliminary data sheet vct 38xxa/b micronas 21 fig. 2 ? 16: digital color transient improvement 2.9.8. inverse matrix a 6-multiplier matrix transcodes the c r and c b signals to r-y, b-y, and g-y. the multipliers are also used to adjust color saturation in the range of 0 to 2. the coef- ficients are signed and have a resolution of 9 bits. there are separate matrix coefficients for main and side pictures. the matrix computes: r ? y = mr1*c b + mr2*c r g ? y = mg1*c b + mr2*c r b ? y = mb1*c b + mr2*c r the initialization values for the matrix are computed from the standard itur (ccir) matrix: for a contrast setting of ctm + 32, the matrix values are scaled by a factor of 64 (see table 2 ? 4 on page 32). 2.9.9. rgb processing after adding the post-processed luma, the digital rgb signals are limited to 10 bits. three multipliers are used to digitally adjust the white drive. using the same multipliers an average beam current limiter is imple- mented (see section 2.10.1. on page 24). 2.9.10. osd color look-up table the vct 38xxa/b has five input lines for an osd sig- nal. this signal forms a 5-bit address for a color look-up table (clut). the clut is a memory with 32 words where each word holds a rgb value. bits 0 to 3 (bit 4 = 0) form the addresses for the rom part of the osd, which generates full rgb signals (bit 0 to 2) and half-contrast rgb signals (bit 3). bit 4 addresses the ram part of the osd with 16 freely programmable colors, addressable with bit 0 to 3. the programming is done via the i 2 c bus. the amplitude of the clut output signals can be adjusted separately for r, g, and b via the i 2 c bus. the switchover between video rgb and osd rgb is done via the priority decoder. 2.9.11. picture frame generator when the picture does not fill the total screen (height or width too small) it is surrounded with black areas. these areas (and more) can be colored with the pic- ture frame generator. this is done by switching over the rgb signal from the matrix to the signal from the osd color look-up table. the width of each area (left, right, upper, lower) can be adjusted separately. the generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. this means, it runs during horizontal, respectively vertical flyback. the color of the complete border can be stored in the programmable osd color look-up table in a separate address. the format is 3 x 4-bit rgb. the contrast can be adjusted separately. the picture frame generator includes a priority master circuit. its priority is programmable and the border is generated only if the priority is higher than the priority of the other sources (video/osd). therefore, the bor- der can be underlay or overlay depending on the pic- ture source. a) c r c b input of dti b) c r c b input + correction signal c) sharpened and limited c r c b t t t c r in c b in a) b) ampl. c r out c b out c) r g b = 1 1 1 0 ? 0.345 1.773 1.402 ? 0.713 0 y c b c r
vct 38xxa/b preliminary data sheet 22 micronas 2.9.12. priority decoder the priority decoder selects the picture source depending on the programmed priorities. up to eight levels can be selected for osd and the picture frame ? where 0 is the highest. the video source always has the lowest priority. a 5-bit information is attached to each priority (see table 2 ? 4 on page 32). these bits are programmable via the i 2 c bus and have the follow- ing meanings: ? one of two contrast, brightness and matrix values for main and side picture ? rgb from video signal or color look-up table ? disable/enable black-level expander ? disable/enable peaking transient suppression when signal is switched ? disable/enable analog fast-blank input 2.9.13. scan velocity modulation picture tubes equipped with an appropriate yoke can use the scan velocity modulation signal to vary the speed of the electron gun during the entire video scan line dependent upon its content. transitions from dark to bright will first speed up and then slow down the scan; vice versa for the opposite transition (see fig. 2 ? 17). the signal delay is adjustable by 3.5 clocks in half- clock steps in respect to the analog rgb output sig- nals. this is useful to match the different groupdelay of analog rgb amplifiers to the one for the svm yoke current. fig. 2 ? 17: svm signal waveform 2.9.14. display phase shifter a phase shifter is used to partially compensate the phase differences between the video source and the flyback signal. by using the described clock system, this phase shifter works with an accuracy of approxi- mately 1 ns. it has a range of 1 clock period which is equivalent to 24.7 ns at 20.25 mhz. the large amount of phase shift (full clock periods) is realized in the front-end circuit. t ampl. beam current svm yoke current
preliminary data sheet vct 38xxa/b micronas 23 fig. 2 ? 18: digital back-end contrast dynamic peaking brightness + offset softlimiter white-drive measurement c lock horizontal flyback dti (c r ) dti (c b ) interpol 4:4:4 black- level expander dig. rout dig. gout dig. bout cr cb dig. y in dig. c r c b in matrix saturation white-drive r x beam curr. lim. display & clock control prio in prio decoder select coefficients main picture side picture matrix r ? matrix g ? matrix b ? y r g b luma insert for crtmeasurement clut, for crt measurement blanking dig. osd in contrast svmout scan velocity modulation picture frame generator prio prio white-drive g x beam curr. lim. white-drive x beam curr. lim. phase shift 0...1 clock phase shift 0...1 clock phase shift 0...1 clock
vct 38xxa/b preliminary data sheet 24 micronas 2.10. video back-end the digital rgb signals are converted to analog rgbs using three video digital-to-analog converters (dac) with 10-bit resolution. an analog brightness value is provided by three additional dacs. the adjustment range is 40% of the full rgb range. controlling the white-drive/analog brightness and also the external contrast and brightness adjustments is done via the fast processor, located in the front-end. control of the cutoff dacs is done via i 2 c bus regis- ters. finally cutoff and blanking values are added to the rgb signals. cutoff (dark current) is provided by three 9-bit dacs. the adjustment range is 60% of full scale rgb range. the analog rgb-outputs are current outputs with cur- rent-sink characteristics. the maximum current drawn by the output stage is obtained with peak white rgb. an external half contrast signal can be used to reduce the output current of the rgb outputs to 50%. 2.10.1. crt measurement and control the display processor is equipped with an 8-bit pdm-adc for all measuring purposes. the adc is connected to the sense input pin, the input range is 0 to 1.5 v. the bandwidth of the pdm filter can be selected; it is 40/80 khz for small/large bandwidth set- ting. the input impedance is more than 1 m ? . cutoff and white-drive current measurement are car- ried out during the vertical blanking interval. they always use the small bandwidth setting. the current range for the cutoff measurement is set by connecting a sense resistor to the madc input. for the white-drive measurement, the range is set by using another sense resistor and the range select switch 2 output pin (rsw2). during the active picture, the minimum and maximum beam current is measured. the measure- ment range can be set by using the range select switch 1 pin (rsw1) as shown in fig. 2 ? 19 and fig. 2 ? 20. the timing window of this measurement is pro- grammable. the intention is, to automatically detect letterbox transmission or to measure the actual beam current. all control loops are closed via the external control microprocessor. fig. 2 ? 19: madc range switches fig. 2 ? 20: madc measurement timing a d madc beam current sense rsw1 rsw2 r3 r2 r1 lines active measure- ment resistor ultra black black r1 || r2 || r3 rsw1=on, rsw2=on picture meas. pmso r1 cb + ibrm b cutoff cr + ibrm + wdrv ? wdr cr + ibrm cg + ibrm g cutoff r cutoff r1 || r3 r1 || r2 || r3 rsw1=on, rsw2=on picture meas. pmst tml rsw2 =on tube measurement r g b white drive r
preliminary data sheet vct 38xxa/b micronas 25 in each field two sets of measurements can be taken: a) the picture tube measurement returns results for ? cutoff r ? cutoff g ? cutoff b ? white-drive r or g or b (sequentially) b) the picture measurement returns data on ? active picture maximum current ? active picture minimum current the tube measurement is automatically started when the cutoff blue result register is read. cutoff control for rgb requires one field only, whereas a complete white-drive control requires three fields. if the mea- surement mode is set to ? offset check ? , a measurement cycle is run with the cutoff/white-drive signals set to zero. this allows to compensate the madc offset as well as input the leakage currents. during cutoff and white-drive measurements, the average beam current limiter function (see section 2.10.3. on page 26) is switched off and a programmable value is used for the brightness setting. the start line of the tube measure- ment can be programmed via i 2 c bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line. the picture measurement must be enabled by the con- trol microprocessor after reading the min./max. result registers. if a ? 1 ? is written into bit 2 in subaddress 25, the measurement runs for one field. for the next mea- surement a ? 1 ? has to be written again. the measure- ment is always started at the beginning of active video. the vertical timing for the picture measurement is pro- grammable, and may even be a single line. also the signal bandwidth is switchable for the picture measure- ment. two horizontal windows are available for the picture measurement. the large window is active for the entire active line. tube measurement is always carried out with the small window. measurement windows for pic- ture and tube measurement are shown in fig. 2 ? 21. fig. 2 ? 21: windows for tube and picture measure- ments 2.10.2. scart output signal the rgb output of the vct 38xxa/b can also be used to drive a scart output. in the case of the scart signal, the parameter clmpr (clamping reference) has to be set to 1. then, during blanking, the rgb out- puts are automatically set to 50% of the maximum brightness. the dc offset values can be adjusted with the cutoff parameters cr, cg, and cb. the ampli- tudes can be adjusted with the drive parameters wdr, wdg, and wdb. active video field 1/ 2 tube measurement picture meas. start picture meas. end small window for tube measurement (cutoff, white drive) large window for active picture picture meas. start
vct 38xxa/b preliminary data sheet 26 micronas 2.10.3. average beam current limiter the average beam current limiter (bcl) uses the sense input for the beam current measurement. the bcl uses a different filter to average the beam current during the active picture. the filter bandwidth is approx. 2 khz. the beam current limiter has an auto- matic offset adjustment that is active two lines before the first cutoff measurement line. the beam current limiter function is located in the front-end. the data exchange between the front-end and the back-end is done via a single-wire serial inter- face. the beam current limiter allows the setting of a thresh- old current. if the beam current is above the threshold, the excess current is low-pass filtered and used to attenuate the rgb outputs by adjusting the white-drive multipliers for the internal (digital) rgb signals, and the analog contrast multipliers for the analog rgb inputs, respectively. the lower limit of the attenuator is programmable, thus a minimum contrast can always be set. during the tube measurement, the abl attenu- ation is switched off. after the white-drive measure- ment line it takes 3 lines to switch back to bcl limited drives and brightness. typical characteristics of the abl for different loop gains are shown in fig. 2 ? 22; for this example the tube has been assumed to have square law characteristics. fig. 2 ? 22: beam current limiter characteristics: beam current output vs. drive bcl threshold: 1 2.10.4. analog rgb insertion the vct 38xxa/b allows insertion of external analog rgb signals. the rgb signal is key-clamped and inserted into the main rgb by the fast-blank switch. the external rgb input can be overlaid or underlaid to the digital picture. the external rgb signals can be adjusted independently as regards dc level (bright- ness) and magnitude (contrast). all signals for analog rgb insertion (rin, gin, bin, fblin) must be synchronized to the horizontal flyback, otherwise a horizontal jitter will be visible. the vct 38xxa/b has no means for timing correction of the analog rgb input signals. 2.10.5. fast-blank monitor the presence of external analog rgb sources can be detected by means of a fast-blank monitor. the status of the fast-blank input can be monitored via an i 2 c bus register. there is a 2 bit information, giving static and dynamic indication of a fast-blank signal. the static bit is directly reading the fast-blank input line, whereas the dynamic bit is reading the status of a flip-flop triggered by the negative edge of the fast- blank signal. with this monitor logic it is possible to detect if there is an external rgb source active and if it is a full screen insertion or only a box. the monitor logic is connected directly to the fblin pin.
preliminary data sheet vct 38xxa/b micronas 27 fig. 2 ? 23: video back-end ext. contrast * white drive r * beam current lim. cutoff r dac video blank & timing adc measurm. u/i-dac clamp key analog r in sense analog r out analog g out analog b out analog g in analog b in measurement buffer digital r in hv measurem. dac ext. brightness * white drive r digital g in digital b in dac dac video dac video u/i-dac u/i-dac cutoff g dac cutoff b dac dac dac input i/o ext. brightness * white drive g ext. brightness * white drive b dac white drive g dac int. brightness * white drive b dac white drive r int. brightness * int. brightness * fast ext. contrast * white drive g * beam current lim. ext. contrast * white drive b * beam current lim. analog svm out dac svm i 0 digital svm in serial interface clamp clamp blank in blanking blanking blanking ext. brightness ext. contrast int . brightness white drive b white drive g white drive r
vct 38xxa/b preliminary data sheet 28 micronas 2.11. synchronization and deflection the synchronization and deflection processing is dis- tributed over front-end and back-end. the video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front-end. most of the processing that runs at the horizontal frequency is programmed on the internal fast processor (fp). also the values for vertical and east/west deflection are calculated by the fp soft- ware. the generation of horizontal and vertical drive signals can be synchronized to the video timing extracted in the front-end or to a free running line counter in the back-end. 2.11.1. deflection processing the deflection processing generates the signals for the horizontal and vertical drive (see fig. 2 ? 24). this block contains two phase-locked loops: ? pll2 generates the horizontal and vertical timing, e.g. blanking, clamping and composite sync. phase and frequency are synchronized by the front sync signal. ? pll3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal out- put stage. phase and frequency are synchronized by the oscillator signal of pll2. the horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse hout. the generator runs at 1 mhz. under control of the ehpll bit and the internal voltage supervision it is either synchronized by the deflection pll or it is free running. in the output stage the fre- quency is divided down to give drive-pulse period and width. the drive pulse width is programmable. the horizontal drive uses an open drain output transistor. after power on or during reset the hout generation is switched to a free running mode with a fix duty cycle of 50%. for normal operation the ehpll bit has to be set first. during the switch the actual period of hout can vary by up to 1 s. 2.11.2. angle and bow correction the angle and bow correction is part of the horizontal drive pll. this feature allows a shift of the horizontal drive pulse phase depending on the vertical position on the screen. the phase correction has a linear (angle) and a quadratic term (bow). 2.11.3. horizontal phase adjustment this section describes a simple way to align pll phases and the horizontal frame position. 1. with hdrv the duration of the horizontal drive pulse has to be adjusted 2. with pofs2 the delay between input video and dis- play timing (e.g. clamping pulse for analog rgb) has to be adjusted 3. with csydel the delay between video and analog rgb (osd) has to be adjusted. 4. with csydel and hpos the horizontal position of both, the digital and analog rgb signal (from scart) relative to the clamping pulse has to be adjusted to the correct position, e.g. the pedestal of the generator signal. 5. with pofs3 the position of horizontal drive/flyback relative to rgb has to be adjusted 6. with newlin the position of a scaled video picture can be adjusted (left, middle, center, etc; versions with panorama scaler only). 7. with hbst and hbso, the start and stop values for the horizontal blanking have to be adjusted. note: the processing delay of the internal digital video path differs depending on the comb filter option of the vct 38xxa/b. the versions with comb filter have an additional delay of 34 clock cycles.
preliminary data sheet vct 38xxa/b micronas 29 fig. 2 ? 24: deflection processing block diagram 2.11.4. vertical and east/west deflection the calculations of the vertical and east/west deflec- tion waveforms is done by the internal fast processor (fp). the algorithm uses a chain of accumulators to generate the required polynomial waveforms. to pro- duce the deflection waveforms, the accumulators are initialized at the beginning of each field. the initializa- tion values must be computed by the tv control pro- cessor and are written to the front-end once. the waveforms are described as polynomials in x, where x varies from 0 to 1 for one field. p: a + b (x-0.5) + c (x-0.5) 2 + d (x-0.5) 3 + e (x-0.5) 4 the initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for east/west deflection are 12-bit values. fig. 2 ? 25 shows several vertical and east/west deflec- tion waveforms. the polynomial coefficients are also stated. in order to get a faster vertical retrace timing, the out- put impedance of the vertical d/a-converter can be reduced by 50% during the retrace. 2.11.5. eht compensation the vertical waveform can be scaled according to the average beam current. this is used to compensate the effects of electric high-tension changes due to beam current variations. eht compensation for east/west deflection is done with an offset corresponding to the average beam current. phase comparator & low-pass pll2 e/w correction sawtooth pwm 15-bit ew vert vprot pwm 15-bit dco front sync interface fsy vdata main sync generator vertical data phase comparator & low-pass pll3 1:64 & output stage hflb hout dco display timing line counter blanking, clamping, etc. clock & control sinewave generator & dac lpf msy vertical reset skew measure- ment angle & bow + vertq sync generation intlc
vct 38xxa/b preliminary data sheet 30 micronas 2.11.6. protection circuitry picture tube and drive stage protection is provided through the following measures: ? vertical flyback protection input: this pin searches for a negative edge in every field, otherwise the rgb drive signals are blanked. ? drive shutoff during flyback: this feature can be selected by software. ? safety input pin: this input has two thresholds. between zero and the lower threshold, normal functioning takes place. between the lower and the higher threshold, the rgb signals are blanked. above the higher thresh- old, the rgb signals are blanked and the horizontal drive is shut off. both thresholds have a small hys- teresis. ? 2.12. reset function reset of all vdp functions is performed by the resq pin. when this pin becomes active, all internal regis- ters and counters are lost. the tv controller can acti- vate the resq pin by software (see section 5.7.2. on page 95). when the resq pin is released, the internal reset is still active for 4 s. after that time, the initialization of all required registers is performed by the internal fast processor. this takes approximately 60 s. during this initialization procedure it is not possible to access the vdp via the i 2 c interface. the vdp voltage supervision activates an internal reset signal when the supply for the digital circuits (vsup d ) goes below ~2.5 v for more than 50 ns. this reset signal may be observed by the cpu (see section 5.7.3. on page 96). fig. 2 ? 25: vertical and east/west deflection waveforms a,b,c,d,e 0,0,1,0,0 0,0,0,0,1 0,0,1,1,1 east/west: a,b,c,d 0,1,0,0 0,1,1,0 0,1,0,1 vertical:
preliminary data sheet vct 38xxa/b micronas 31 2.14. i 2 c bus slave interface communication between the video processing part of the vdp and the cpu is done via i 2 c bus. for detailed information on the i 2 c bus please refer to the philips manual ? i 2 c bus specification ? . the vdp has two i 2 c bus slave interfaces (for compat- ibility with vpc/ddp applications) ? one in the front-end and one in the back-end. both i 2 c bus inter- faces use i 2 c clock synchronization to slow down the interface if required. both i 2 c bus interfaces use one level of subaddress: the i 2 c bus chip address is used to address the vdp and a subaddress selects one of the internal registers. the i 2 c bus chip addresses are given below: the registers of the vdp have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. fig. 2 ? 26 shows i 2 c bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. 2.14.1. control and status registers ta b le 2 ? 3 gives definitions of the vdp control and sta- tus registers. the number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 msb will be ? don ? t care ? on write operations and ? 0 ? on read opera- tions. write registers that can be read back are indi- cated in table 2 ? 3. functions implemented by software in the on-chip con- trol microprocessor (fp) are explained in table 2 ? 7. a hardware reset initializes all control registers to 0. the automatic chip initialization loads a selected set of registers with the default values given in table 2 ? 3. the register modes given in table 2 ? 3 are ? w: write only register ? w/r: write/read data register ? r: read data from vdp ? v: register is latched with vertical sync ? h: register is latched with horizontal fig. 2 ? 26: i 2 c bus protocols table 2 ? 2: i 2 c chip addresses chip address a6 a5 a4 a3 a2 a1 a0 r/w front-end 10001111/0 back-end 10001011/0 p s 1 0 sda scl s s 1000 111 1000 111 wack ack w 0111 1100 0111 1100 ack ack s 1 or 2 byte data 1000 111 r high byte data low byte data p w r ack nak s p = = = = = = 0 1 0 1 start stop ack nak p i 2 c write access subaddress 7c i 2 c read access subaddress 7c
vct 38xxa/b preliminary data sheet 32 micronas table 2 ? 3: i 2 c control and status registers of the video front-end i 2 c sub address number of bits mode function default name fp interface h ? 35 8 r fp status bit [0] write request bit [1] read request bit [2] busy fpsta h ? 36 16 w bit[8:0] 9-bit fp read address bit[11:9] reserved, set to zero fprd h ? 37 16 w bit[8:0] 9-bit fp write address bit[11:9] reserved, set to zero fpwr h ? 38 16 w/r bit[11:0] fp data register, reading/writing to this register will autoincrement the fp read/ write address. only 16 bit of data are transferred per i 2 c telegram. fpdat black line detector h ? 12 16 r available for versions with panorama scaler only! read only register, do not write to this register! after reading, lowlin and uplin are reset to 127 to start a new measurement bit[6:0] number of lower black lines bit[7] always 0 bit[14:8] number of upper black lines bit[15] normal/black picture blklin lowlin uplin blkpic miscellaneous h ? 29 16 w/r test pattern generator: bit[10:0] reserved (set to 0) bit[11] 0/1 disable/enable test pattern generator bit[13:12] output mode: 00 y/c = ramp (240 ... 17) 01 y/c = 16 10 y/c = 90 11 y/c = 240 bit[15:14] 0/1 reserved (set to 0) 0 0 0 0 tpg tpgen tpgmode h ? 22 16 w/r newline: available for versions with panorama scaler only! bit[10:0] newline register this register defines the readout start of the next line in respect to the value of the sync counter. bit [15:11] reserved (set to 0) 0 newlin table 2 ? 4: i 2 c control and status registers of the video back-end. ? default values are initialized at reset i 2 c sub address number of bits mode function default name luminance channel h ? 61 9 w v bit [5:0] 0..63/32 main picture contrast 32 ctm
preliminary data sheet vct 38xxa/b micronas 33 h ? 65 9 w v bit [5:0] 0..63/32 side picture contrast 32 cts h ? 51 9 w v bit [8:0] ? 256..255 main picture brightness 0 brm h ? 55 9 w v bit [8:0] ? 256..255 side picture brightness 0 brs h ? 75 9 w v luma channel, priority mask register bit [7:0] 0/1 select contrast, brightness, matrix for main/side picture 0 pbct 1) h ? 71 9 w v luma channel, priority mask register bit [7:0] 0/1 select main (video) / external (via clut) rgb 0 pbergb 1) black-level expander h ? 59 9 w v black-level expander bit [3:0] 0..15 tilt coefficient bit [8:4] 0...31 amount 8 12 ble1 btlt bam h ? 5d 9 w v black-level expander, threshold: bit [8:0] 0..511 disable expansion, threshold value 200 ble2 bthr h ? 73 9 w v black-level expander, measurement bit [7:0] 0..255 vstart/2 start line = vstart stop line = 336/283 ? vstart or vertical blanking bit[8] 0/1 50/60 hz measurement windowlength 15 0 ble3 bvst bwl h ? 7d 9 w v black-level expander, priority mask register bit [7:0] 0/1 enable/disable black-level expander 0 pbble 1) dynamic peaking h ? 69 9 w v luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8 bit [3:0] 0..15 k1: peaking level undershoot bit [7:4] 0..15 k2: peaking level overshoot bit [8] 0/1 peaking value normal/inverted (peaking/softening) 4 4 0 pk1 pkun pkov pkinv h ? 6d 9 w v luma peaking filter, coring bit [4:0] 0..31 coring level bit [7:5] reserved bit [8] 0/1 peaking filter center frequency high/ low 3 0 pk2 cor pfs h ? 79 9 w v luma peaking filter, priority mask register bit [7:0] 0/1 disable/enable peaking transient suppression when signal is switched 0 pbpk 1) 1) priority mask register if bit[x] is set to 1 then the function is active for the respective signal priority table 2 ? 4: i 2 c control and status registers of the video back-end. ? default values are initialized at reset i 2 c sub address number of bits mode function default name
vct 38xxa/b preliminary data sheet 34 micronas soft limiter h ? 41 9 w v luma soft limiter, slope a and b bit [3:0] slope segment a bit [7:4] slope segment b 0 0 lsl1 lslsa lslsb h ? 45 9 w v luma soft limiter, absolute limit bit [7:0] luma soft limiter absolute limit (unsigned) bit [8] 0/1 modulation off/on 255 1 lsl2 lslal lslm h ? 49 9 w v bit [8:0] luma soft limiter segment b tilt point (unsigned) 300 lsltb h ? 4d 9 w v bit [8:0] luma soft limiter segment a tilt point (unsigned) 250 lslta chrominance channel h ? 14 8 w/r luma/chroma matching bit [2:0] ? 3...3 variable chroma delay bit [7:3] reserved, set to 0 0 lcm cdel h ? 5e 9 w v digital transient improvement bit [3:0] 0..15 coring value bit [7:4] 0..15 dti gain bit [8] 0/1 narrow/wide bandwidth mode 1 5 1 dti dtico dtiga dtimo inverse matrix h ? 7c h ? 74 9 9 w v w v main picture matrix coefficient r ? y = mr1m*c b + mr2m*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 0 86 mr1m, mr2m h ? 6c h ? 64 9 9 w v w v main picture matrix coefficient g ? y = mg1m*c b + mg2m*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 ? 22 ? 44 mg1m, mg2m h ? 5c h ? 54 9 9 w v w v main picture matrix coefficient b ? y = mb1m*c b + mb2m*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 113 0 mb1m, mb2m h ? 78 h ? 70 9 9 w v w v side picture matrix coefficient r ? y = mr1s*c b + mr2s*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 0 73 mr1s, mr2s h ? 68 h ? 60 9 9 w v w v side picture matrix coefficient g ? y = mg1s*c b + mg2s*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 ? 19 ? 37 mg1s, mg2s h ? 58 h ? 50 9 9 w v w v side picture matrix coefficient b ? y = mb1s*c b + mb2s*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 97 0 mb1s, mb2s table 2 ? 4: i 2 c control and status registers of the video back-end. ? default values are initialized at reset i 2 c sub address number of bits mode function default name
preliminary data sheet vct 38xxa/b micronas 35 color lookup table h ? 00 ? h ? 0f 16 w h color look-up table: 16 entries, 12 bit wide, the clut registers are initialized at power-up bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 000h f00h 0f0h ff0h 00fh f0fh 0ffh fffh 7ffh 700h 070h 770h 007h 707h 077h 777h clut0 clut15 h ? 4c 9 w v digital osd insertion contrast for r (amplitude range: 0 to 255) bit [3:0] 0..13 r amplitude = clutn ? (drct + 4) 14,15 invalid picture frame insertion contrast for r (ampl. range: 0 to 255) bit [7:4] 0..13 r amplitude = pfcr ? (pfrct + 4) 14,15 invalid 8 8 rct drct pfrct h ? 48 9 w v digital osd insertion contrast for g (amplitude range: 0 to 255) bit [3:0] 0..13 g amplitude = clutn ? (dgct + 4) 14,15 invalid picture frame insertion contrast for g (ampl. range: 0 to 255) bit [7:4] 0..13 g amplitude = pfcg ? (pfgct + 4) 14,15 invalid 8 8 gct dgct pfgct h ? 44 9 w v digital osd insertion contrast for b (amplitude range: 0 to 255) bit [3:0] 0..13 b amplitude = clutn ? (dbct + 4) 14,15 invalid picture frame insertion contrast for b (ampl. range: 0 to 255) bit [7:4] 0..13 b amplitude = pfcb ? (pfbct + 4) 14,15 invalid 8 8 bct dbct pfbct picture frame generator h ? 11 16 w/r picture frame color bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 0 0 0 pfc pfcb pfcg pfcr h ? 47 9 w v bit [2:0] picture frame generator priority id bit [8] enable prio id for picture frame generator 0pfgid pfgen h ? 4f 9 w v bit [8:0] horizontal picture frame begin code 0 = picture frame generator horizontally disabled code 1ff = full frame 0pfghb h ? 53 9 w v bit [8:0] horizontal picture frame end 0 pfghe h ? 63 9 w v bit [8:0] vertical picture frame begin code 0 = picture frame generator vertically disabled 270 pfgvb table 2 ? 4: i 2 c control and status registers of the video back-end. ? default values are initialized at reset i 2 c sub address number of bits mode function default name
vct 38xxa/b preliminary data sheet 36 micronas h ? 6f 9 w v bit [8:0] vertical picture frame end 56 pfgve scan velocity modulation h ? 5a 9 w v video mode coefficients bit [5:0] gain1 bit [8:6] differentiator delay 1 (0= filter off, 1...6= delay) 60 4 svm1 svg1 svd1 h ? 56 9 w v text mode coefficients bit [5:0] gain 2 bit [8:6] differentiator delay 2 (0= filter off, 1...6= delay) 60 4 svm2 svg2 svd2 h ? 52 9 w v limiter bit [6:0] limit value bit [8:5] not used, set to ? 0 ? 100 0 svm3 svlim h ? 4e 9 w v delay and coring bit [3:0] adjustable delay, in 1/2 display clock steps, (value 5 : delay of svmout is the same as for rgbout bit [7:4] coring value bit [8] not used, set to ? 0 ? 7 0 svm4 svdel svcor display controls h ? 4a h ? 46 h ? 42 9 9 9 w v w v w v cutoff red cutoff green cutoff blue 0 0 0 cr cg cb tube- and picture-measurements h ? 7b 9 w v picture measurement start line bit [8:0] (tml+9)..511 first line of picture measurement 23 pmst h ? 6b 9 w v picture measurement stop line bit [8:0] (pmst+1)..511 last line of picture measurement 308 pmso h ? 7f 9 w v tube measurement line bit [8:0] 0..511 start line for tube measurement 15 tml h ? 25 8 w/r tube and picture measurement control bit [0] 0/1 disable/enable tube measurement bit [1] 0/1 80/40 khz bandwidth for picture measurement bit [2] 0/1 disable/enable picture measurement (writing a ? 1 ? starts one measurement cycle) bit [3] 0/1 large/small picture measurement window, will be disabled from bit[3] in address h ? 32 bit [4] 0/1 measure / offset check for adc bit [7:5] reserved 0tpm tmen pmbw pmen pmwin ofsen h ? 13 16 w/r white drive measurement control bit [9:0] 0..1023 rgb values for white drive beam current measurement bit [10] reserved bit [11] 0/1 rgb values for white drive beam current measurement disabled/enabled 512 0 wdm wdrv ewdm table 2 ? 4: i 2 c control and status registers of the video back-end. ? default values are initialized at reset i 2 c sub address number of bits mode function default name
preliminary data sheet vct 38xxa/b micronas 37 h ? 18 h ? 19 h ? 1a h ? 1d h ? 1c h ? 1b 8 r measurement result registers minimum in active picture maximum in active picture white drive cutoff/leakage red cutoff/leakage green cutoff/leakage blue, read pulse starts tube measurement ? mrmin mrmax mrwdr mrcr mrcg mrcb h ? 1e 8 r measurement adc status and fast-blank input status measurement status register bit [0] 0/1 tube measurement active / complete bit [2:1] white drive measurement cycle 00 red 01 green 10 blue 11 reserved bit [3] 0/1 picture measurement active / complete bit [4] 0/1 fast-blank input low / high (static) bit [5] 1 fast-blank input negative transition since last read (bit reset at read) bit [7:6] reserved ? pms tums wdrmc pims fblev fbslo vertical timing h ? 67 9 w v vertical blanking start bit [8:0] 0..511 first line of vertical blanking 305 vbst h ? 77 9 w v vertical blanking stop bit [8:0] 0..511 last line of vertical blanking 25 vbso h ? 5f 9 w v vertical free run period bit [8:0] free running field period = (value+4) lines 309 vper horizontal deflection and timing h ? 7a 9 w v quadratic term of angle & bow correction bit [8:0] ? 256..+255 ( 500 ns) 0bow h ? 76 9 w v linear term of angle & bow correction bit [8:0] ? 256..+255 ( 500 ns) 0angle h ? 6e 9 w v adjustable delay of pll2, clamping, and blanking (relative to front sync) adjust clamping pulse for analog rgb input bit [8:0] ? 256..+255 ( 8 s) ? 141 pofs2 h ? 72 9 w v adjustable delay of flyback, main sync, csync and analog rgb (relative to pll2) adjust horizontal drive or csync bit [8:0] ? 256..+255 ( 8 s) 0pofs3 h ? 7e 9 w v adjustable delay of main sync (relative to flyback) adjust horizontal position for digital picture bit [8:0] 20 steps = 1 s 120 hpos table 2 ? 4: i 2 c control and status registers of the video back-end. ? default values are initialized at reset i 2 c sub address number of bits mode function default name
vct 38xxa/b preliminary data sheet 38 micronas t h ? 5b 9 w v start of horizontal blanking bit [8:0] 0..511 1hbst h ? 57 9 w v end of horizontal blanking bit [8:0] 0..511 48 hbso h ? 62 h ? 66 h ? 6a 9 9 9 w v w v w v pll2/3 filter coefficients, 1of5 bit code (n + set bit number) bit [5:0] proportional coefficient pll3, 2 ? n ? 1 bit [5:0] proportional coefficient pll2, 2 ? n ? 1 bit [5:0] integral coefficient pll2, 2 ? n ? 5 2 1 2 pkp3 pkp2 pki2 h ? 15 16 w/r horizontal drive and vertical signal control register bit [5:0] 0..63 horizontal drive pulse duration in s (internally limited to 4..61) bit [6] 0/1 disable/enable horizontal pll2 and pll3 bit [7] 0/1 1: disable horizontal drive pulse during flyback bit [8] reserved, set to ? 0 ? bit [9] 0/1 enable/disable ultra black blanking bit [10] 0/1 0: all outputs blanked 1: normal mode bit [11] 0/1 enable/disable clamping for analog rgb input bit [12] 0/1 disable/enable vertical free running mode (field is set to field2, no interlace) bit [13] 0/1 enable/disable vertical protection bit [14] reserved, set to ? 0 ? bit [15] 0/1 disable/enable phase shift of display clock 32 0 0 0 0 1 0 0 0 0 1 hvc hdrv ehpll eflb dubl ebl dcrgb selft dvpr diska h ? 9d 8 w/r sync output control bit [0] invert intlc bit [4:1] reserved, set to ? 0 ? bit [5] force intlc to polarity defined in ? intlcinv ? 0 syctrl intlcinv intl- cfrc miscellaneous h ? 32 8 w/r fast-blank interface mode bit [0] 0 internal fast-blank from fblin pin 1 force internal fast-blank signal to high bit [1] 0/1 internal fast-blank active high/low bit [2] 0/1 disable/enable clamping reference for rgb outputs bit [3] 1 full line madc measurement window, disables bit [3] in address h ? 25 bit [4] 0/1 horizontal flyback input active high/low bit [6:5] reserved (set to 0) bit [7] vertical output select 0 vertq output 1 intlc output 0fbmod fbfoh fbpol clmpr flmw flpol vos h ? 4b 9 w v fast-blank input, priority mask register bit [7:0] 0/1 disable/enable analog fast-blank input 0 pbfb 1) table 2 ? 4: i 2 c control and status registers of the video back-end. ? default values are initialized at reset i 2 c sub address number of bits mode function default name
preliminary data sheet vct 38xxa/b micronas 39 table 2 ? 5: control registers of the fast processor for control of the video front-end functions fp sub- address function default name standard selection h ? 20 standard select: bit[2:0] standard 0 pal b,g,h,i (50 hz) 4.433618 1 ntsc m (60 hz) 3.579545 2 secam (50 hz) 4.286 3 ntsc44 (60 hz) 4.433618 4 pal m (60 hz) 3.575611 5 pal n (50 hz) 3.582056 6 pal 60 (60 hz) 4.433618 7 ntsc comb (60 hz) 3.579545 bit[3] 0/1 standard modifier pal modified to simple pal ntsc modified to compensated ntsc secam modified to monochrome 625 ntscc modified to monochrome 525 bit[4] reserved (set to 0) bit[5] 0/1 2-h comb filter off/on bit[6] 0/1 s-vhs mode off/on (2-h comb is switched off) option bits allow to suppress parts of the initialization, this can be used for color standard search: bit[7] no hpll setup bit[8] no vertical setup bit[9] no acc setup bit[10] 2-h comb filter set-up only bit[11] status bit, normally write 0. after the fp has switched to a new standard, this bit is set to 1 to indicate operation complete. standard is automatically initialized when the insel register is written. 0sdt pal ntsc secam ntsc44 palm paln pal60 ntscc sdtmod comb svhs sdtopt h ? 148 enable automatic standard recognition (asr) bit[0] 0/1 pal b,g,h,i (50 hz) 4.433618 bit[1] 0/1 ntsc m (60 hz) 3.579545 bit[2] 0/1 secam (50 hz) 4.286 bit[3] 0/1 ntsc44 (60 hz) 4.433618 bit[4] 0/1 pal m (60 hz) 3.575611 bit[5] 0/1 pal n (50 hz) 3.582056 bit[6] 0/1 pal 60 (60 hz) 4.433618 bit[10:7] reserved set to 0 bit[11] 1 reset status information ? switch ? in asr_status (cleared automatically) 0: disable recognition; 1: enable recognition note: for correct operation don ? t change fp reg. 20h and 21h, while asr is enabled! 0asr_ena
vct 38xxa/b preliminary data sheet 40 micronas h ? 14e status of automatic standard recognition bit[0] 1 error of the vertical standard (neither 50 nor 60 hz) bit[1] 1 detected standard is disabled bit[2] 1 search active bit[3] 1 search terminated, but failed bit[4] 1 no color found bit[5] 1 standard has been switched (since last reset of this flag with bit[11] of asr_enable) bit[4:0] 00000 all ok 00001 search not started, because vwin error detected (no input or secam l) 00010 search not started, because detected vert. standard not enabled 0x1x0 search started and still active 01x00 search failed (found standard not correct) 01x10 search failed, (detected color standard not enabled) 10000 no color found (monochrome input or switch betw. cvbs/svhs necessary) 0 asr_status vwinerr disabled busy failed nocolor switch h ? 21 input select: writing to this register will also initialize the stan- dard bit[1:0] luma selector 00 vin1 01 vin2 10 vin3 11 vin4 bit[2] chroma selector 0cin1 1cin2 bit[4:3] if compensation 00 off 01 6 db/oct 10 12 db/oct 11 10 db/mhz only for secam bit[6:5] chroma bandwidth selector 00 narrow 01 normal 10 broad 11 wide bit[7] 0/1 adaptive/fixed secam notch filter bit[8] available for versions with panorama scaler only! 0 disable luma lowpass filter 1 enable luma lowpass filter bit[10:9] hpll speed 00 no change 01 terrestrial 10 vcr 11 mixed bit[11] status bit, write 0, this bit is set to 1 to indicate operation complete. 00 0 00 01 insel vis cis ifc cbw fntch lowp hpllmd h ? 22 available for versions with panorama scaler only! picture start position, this register sets the start point of active video, this can be used e.g. for panning. the setting is updated when ? sdt ? register is updated. 0sfif table 2 ? 5: control registers of the fast processor for control of the video front-end functions fp sub- address function default name
preliminary data sheet vct 38xxa/b micronas 41 h ? 23 luma/chroma delay adjust. the setting is updated when ? sdt ? register is updated. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... ? 7 0ldly h ? 2f yc r c b mode control register bit[3:0] reserved (set to 0) bit[4] available on vct 38xxb only! 0 disable yc adder 1 enable yc adder bit[5] available on vct 38xxb only! 0 video input 5 disable (pin p10 = p10) 1 video input 5 enable (pin p10 = vin5) bit[6] available on vct 38xxb only! 0 video input = vin1-4 (depending on vis setting) 1 video input = vin5 bit[7] clipping due to adc over-/underflow (has to be reset after read if used) bit[8] 0 disable yc r c b 1 enable yc r c b bit[9] adc range 0 nominal input amplitude ( 350 mv) 1 extended input amplitude ( 500 mv) bit[11:10] reserved (set to 0) note: activate the yc r c b mode by ? enabling yc r c b ? selecting simple pal or ntsc m, svhs=1, comb=0 in the std register ? setting cbw=2 in the insel register 0yc r c b ycadd vin5en vin5sel adcclip yc r c b _en adcr comb filter h ? 27 comb filter control register bit[0] 0 comb coefficients are calculated for luma/chroma 1 comb coefficients for luma are used for luma and chroma bit[1] 0 luma comb strength depends on signal amplitude 1 luma comb strength is independent of amplitude bit[2] 0 reduced comb booster 1 max comb booster bit[4:3] 0..3 comb strength for chroma signal bit[6:5] 0..3 comb strength for luma signal bit[11:7] 0..31 overall limitation of the calculated comb coefficients 0 no limitation 31 max limitation (1/2) 0 0 1 3 2 0 cmb_uc cc daa kb kc ky clim color processing h ? 30 saturation control bit[11:0] 0...4094 (2070 corresponds to 100% saturation) 4095 disabled (test mode only) 2070 acc_sat h ? 17a bit[10:0] 0...2047 cr-attenuation bit[11] 0/1 disable/enable cr-attenuation 1591 o cr_att cr_att_ena h ? 39 bit[10:0] 0...2047 amplitude killer level (0: killer disabled) bit[11] 0/1 disable/enable chroma adc 25 0 kilvl ecadc h ? 3a amplitude killer hysteresis 5 kilhy table 2 ? 5: control registers of the fast processor for control of the video front-end functions fp sub- address function default name
vct 38xxa/b preliminary data sheet 42 micronas h ? dc ntsc tint angle, 512 = /4 0 tint dvco h ? f8 crystal oscillator center frequency adjust, ? 2048 ... 2047 ? 720 dvco h ? f9 crystal oscillator center frequency adjustment value for line-lock mode true adjust value is dvco ? adjust. for factory crystal alignment, using standard video signal: set dvco = 0, set lock mode, read crystal offset from adjust register and use negative value for initial center frequency adjustment via dvco. read only adjust h ? f7 crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked 0xlck h ? b5 crystal oscillator line-locked mode, autolock feature. if autolock is enabled, crystal oscillator locking is started automatically. bit[11:0] threshold; 0: autolock off 400 autolock fp status h ? 12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force bit[8:4] reserved, do not change bit[9] disable flywheel interlace bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0 0 1 gpc vfrc dflw h ? 13 standard recognition status bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] 1 no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[11:10] reserved ? asr h ? 14 input noise level read only noise h ? cb number of lines per field, p/s: 312, n: 262 read only nlpf h ? 15 vertical field counter, incremented per field read only vcnt h ? 74 measured sync amplitude value, nominal: 768 (pal), 732 (ntsc) read only sampl h ? 36 measured burst amplitude read only bampl h ? f0 firmware version number bit[7:0] internal revision number bit[11:8] firmware release read only sw_version table 2 ? 5: control registers of the fast processor for control of the video front-end functions fp sub- address function default name
preliminary data sheet vct 38xxa/b micronas 43 h ? f1 hardware version number bit[6:0] reserved bit[11:7] bond option bit[7] 0/1 16k text memory on/off bit[8] 0/1 vdp platform full/lite bit[9] 0/1 picture improvements on/off bit[10] 0/1 panorama scaler on/off bit[11] 0/1 comb filter on/off read only hw_version h ? 170 status of mcv detection bit[0] agc pulse detected bit[1] pseudo sync detected read only mcv_status h ? 171 bit[11:0] first line of mcv detection window 6 mcv_start h ? 172 bit[11:0] last line of mcv detection window 15 mcv_stop horizontal scaler 1) these registers are updated when the scaler mode register is written h ? 40 scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, ? panorama ? 2 nonlinear scaling mode, ? waterglass ? 3 reserved bit[10:2] reserved, set to 0 bit[11] scaler update 0 start scaler update command, when the registers are updated the bit is set to 1 0scmode mode scup h ? 41 luma offset register 1) bit[6:0] luma offset 0..127 itu-r output format: 57 cvbs output format: 4 57 yoffs h ? 42 active video length for 1-h fifo 1) bit[11:0] length in pixels 1080 fflim h ? 43 scaler1 compression coefficient 1) for compression by a factor c the value c*1024 is required. bit[11:0] allowed values from 1024..4095 1024 scinc1 h ? 44 scaler2 expansion coefficient 1) for expansion by a factor c the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 1024 scinc2 h ? 45 scaler1/2 nonlinear scaling coefficient 1) 0scinc h ? 47 ? h ? 4b scaler1 window controls 1) 5 12-bit registers for control of the nonlinear scaling 0 scw1_0 ? 4 h ? 4c ? h ? 50 scaler2 window controls 1) 5 12-bit registers for control of the nonlinear scaling 0 scw2_0 ? 4 table 2 ? 5: control registers of the fast processor for control of the video front-end functions fp sub- address function default name
vct 38xxa/b preliminary data sheet 44 micronas 2.14.1.1. scaler adjustment in case of linear scaling, most of the scaler registers need not be set. only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. the adjustment of the scaler for nonlinear scaling modes should use the parameters given in table 2 ? 6. table 2 ? 6: set-up values for nonlinear scaler modes register scaler modes ? waterglass ? border 35% ? panorama ? border 30% center compression 3/4 5/6 4/3 6/5 scinc1 1643 1427 1024 1024 scinc2 1024 1024 376 611 scinc 90568556 fflim 945 985 921 983 scw1 ? 0 1101158394 scw1 ? 1 156 166 147 153 scw1 ? 2 317 327 314 339 scw1 ? 3 363 378 378 398 scw1 ? 4 473 493 461 492 scw2 ? 0110115122118 scw2 ? 1 156 166 186 177 scw2 ? 2 384 374 354 363 scw2 ? 3 430 425 418 422 scw2 ? 4 540 540 540 540
preliminary data sheet vct 38xxa/b micronas 45 table 2 ? 7: control registers of the fast processor for controlling the video back-end functions ? default values are initialized at reset fp sub- address function default name fp display control register h ? 130 white drive red (0...1023) 700 wdr 1) h ? 131 white drive green (0...1023) 700 wdg 1) h ? 132 white drive blue (0...1023) 700 wdb 1) h ? 139 internal brightness, picture (0...511), the center value is 256, the range allows for both increase and reduction of brightness. 256 ibr h ? 13c internal brightness, measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff cur- rent. the measurement brightness is independent of the drive values. 256 ibrm h ? 13a analog brightness for external rgb (0...511), the center value is 256, the range allows for both increase and reduction of brightness. 256 abr h ? 13b analog contrast for external rgb (0...511) 350 act 1) the white drive values will become active only after writing the blue value wdb, latching of new values is indi- cated by setting the msb of wdb. fp display control register, bcl h ? 144 bcl threshold current, 0...2047 (max adc output ~1152) 1000 bclthr h ? 142 bcl time constant 0...15 ? 13...1700 msec 15 bcltm h ? 143 bcl loop gain. 0..15 0 bclg h ? 145 bcl minimum contrast 0...1023 307 bclmin h ? 105 test register for bcl/eht comp. function, register value: 0 normal operation 1 stop adc offset compensation x>1 use x in place of input from measurement adc 0bcltst h ? 60 current bcl reduction (0...1023) read only bclreduc fp display control register, deflection h ? 103 interlace offset, ? 2048..2047 this value is added to the sawtooth output during one field. 0intlc h ? 102 discharge sample count for deflection retrace, sawtooth dac output impedance is reduced for dscc lines after ver- tical retrace. 7dscc h ? 11f vertical discharge value, sawtooth output value during discharge operation, typically same as a0 init value for sawtooth. ? 1365 dscv h ? 10b eht compensation vertical gain coefficient, 0...511 0 ehtv h ? 10a eht compensation time constant, 0...15 --> 3.2.410 misc. 15 ehttm h ? 10f eht compensation east/west gain coefficient, ? 1024...1023 15 ehtew
vct 38xxa/b preliminary data sheet 46 micronas 2.14.1.2. calculation of vertical and east-west deflection coefficients in table 2 ? 8 the formula for the calculation of the deflection initialization parameters from the polynomi- nal coefficients a, b, c, d, e is given for the vertical and east-west deflection. let the polynomial be: the initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for east-west deflection are 12-bit values. the coefficients that should be used to calculate the initialization values for different field frequencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 hz vertical deflection is fp display control register, vertical sawtooth h ? 110 dc offset of sawtooth output this offset is independent of eht compensation. 0ofs h ? 11b accu0 init value ? 1365 a0 h ? 11c accu1 init value 900 a1 h ? 11d accu2 init value 0 a2 h ? 11e accu3 init value 0 a3 fp display control register, east-west parabola h ? 12b accu0 init value ? 1121 a0 h ? 12c accu1 init value 219 a1 h ? 12d accu2 init value 479 a2 h ? 12e accu3 init value ? 1416 a3 h ? 12f accu4 init value 1052 a4 table 2 ? 7: control registers of the fast processor for controlling the video back-end functions ? default values are initialized at reset fp sub- address function default name p = a + b(x ? 0.5) + c(x ? 0.5) 2 + d(x ? 0.5) 3 + e(x ? 0.5) 4 a0 = (a 128 ? b 1365.3 + c 682.7 ? d 682.7) / 128
preliminary data sheet vct 38xxa/b micronas 47 table 2 ? 8: calculation of initialization values for vertical sawtooth and east-west parabola vertical deflection 50 hz abcd a0 128 ? 1365.3 +682.7 ? 682.7 a1 899.6 ? 904.3 +1363.4 a2 296.4 ? 898.4 a3 585.9 vertical deflection 60 hz abcd a0 128 ? 1365.3 +682.7 ? 682.7 a1 1083.5 ? 1090.2 +1645.5 a2 429.9 ? 1305.8 a3 1023.5 east-west deflection 50 hz ab c d e a0 128 ? 341.3 1365.3 ? 85.3 341.3 a1 111.9 ? 899.6 84.8 ? 454.5 a2 586.8 ? 111.1 898.3 a3 72.1 ? 1171.7 a4 756.5 east-west deflection 60 hz ab c d e a0 128 ? 341.3 1365.3 ? 85.3 341.3 a1 134.6 ? 1083.5 102.2 ? 548.4 a2 849.3 ? 161.2 1305.5 a3 125.6 ? 2046.6 a4 1584.8
vct 38xxa/b preliminary data sheet 48 micronas 3. text and osd processing 3.1. introduction the vct 38xxa/b includes a world system teletext (wst) decoder, whose display capabilities are also used for osd generation. in the following sections the text and osd processing part of the vct 38xxa/b will be named tpu for short. with integrated cpu, ram and rom, an adaptive data slicer, a display controller, and a number of inter- faces, the tpu offers acquisition and display of various teletext and data services such as wst, pdc, vps, and wss. fig. 3 ? 1 shows the functional block diagram of the tpu. the tpu operates independently from the tv control- ler and can be controlled by software via i 2 c bus inter- face (see section 3.14. on page 85). the tv control- ler is not burdened with the task of teletext decoding and communicates with the tpu via a high-level com- mand language. the tpu performs the following tasks: ? teletext data acquisition (hardware) ? teletext data decoding (software) ? page generation (software) ? page memory management (software) ? page display (hardware) ? user interface (software) 3.2. sram interface the sram interface connects a standard sram to the internal bus structure. the address bus is 19 bit wide, addressing srams up to 4 mbit. smaller srams can also be connected. the sram interface has to handle 3 asynchronous data streams. the cpu needs access to every mem- ory location of the sram. during vbi the slicer writes up to 22 teletext lines of 43 bytes into the acquisition scratch memory. during text display the display con- troller copies teletext rows from display memory into its internal row buffer. on vct 38xxa/b the sram interface of the tpu is connected to the memory bus of the tv controller. this is done to save pins and to give the tv controller faster access to the display memory. refer to dma interface (chapter 5.9. on page 101) for more details. after reset the tpu will not use the sram interface until receiving the i 2 c command ? dram_mode ? (see section 3.12. on page 70). 3.3. text controller the tpu operates with its own 65c02 core running at 10.125 mhz. the core can address up to 64 kbytes of memory. the cpu memory contains 640 bytes ram, 12 kbytes program rom and 12 kbytes character rom. the vct 38xxb contains additional 12kbytes character rom. the character rom holds the font data and is separated from the program rom to save cpu time. the cpu can still access the character rom via a dma interface including wait cycles. the display con- troller can also access the cpu memory via the same dma interface. by this means it is possible to locate part of the character font in program rom or part of the program code in character rom. after reset the cpu switches to external font memory if the font id vector exists in the external font memory. after reset the cpu switches to external program memory if the prog id vector exists in the external pro- gram memory. table 3 ? 1: memory map of text controller memory vector absolute address (high byte, low byte) irq ffff, fffe reset fffd, fffc nmi fffb, fffa control word fff9 prog id (=a55a) fff7, fff6 font id (=a55a) 1001, 1000 memory segment absolute address zero page 0000 ? 00ff stack page 0100 ? 01ff osd buffer 0100 ? 019f i/o page 0200 ? 02ff extra page 0300 ? 037f character rom 5000 ? 7fff ( vct38xxa ) 2000 ? 7fff ( vct38xxb ) program rom d000 ? ffff
preliminary data sheet vct 38xxa/b micronas 49 fig. 3 ? 1: block diagram of the tpu tpu wst layer 65c02 dma interface character rom program rom program ram adc clamping agc i 2 c bus interface timer interrupt watchdog slicer osd layer sync interface color & prio interface sram interface
vct 38xxa/b preliminary data sheet 50 micronas fig. 3 ? 2: memory environment of text controller 3.4. teletext acquisition the only task of the slicer circuit is to extract teletext lines from the incoming composite video signal and to store them into the acquisition scratch buffer of the internal/external sram. no page selection is done at this hardware level. four analog sources can be connected, thus it is pos- sible to receive text from one channel while watching another on the screen. after clamping and agc ampli- fier the analog video signal is converted into binary data. sync separation is done by a sync slicer and a horizontal pll, which generate the horizontal and ver- tical timing. by these means, no external sync signals are needed and any available signal source can be used for teletext reception. the teletext information itself is acquired using adap- tive slicers on bit and byte level with soft error detec- tion to decrease the bit error rate under bad reception conditions. the slicer can be programmed to different bit rates for reception of pal, ntsc or mac world system teletext as well as vps, wss, or caption signals. 3.5. teletext page management as a state-of-the-art teletext decoder, the tpu is able to store and manage a sufficient number of teletext pages to absorb the annoying transmission cycle times. the number of available pages is only limited by the memory size. with an intelligent software and a 4-mbit sram it is possible to store and to control more than 500 teletext pages. the management of such a data base is a typical soft- ware task and is therefore performed by the 65c02. using a fixed length page table with one entry for every possible page, the software distributes the con- tent of the acquisition scratch buffer among the page memory. the page size is fixed to 1 kbyte, only ghost rows are chained in 128-byte segments to avoid unused memory space. a stored teletext page cannot be displayed directly, because of the row-adaptive transmission and the level 2 enhancements (row 26 ? 29). therefore, the cpu has to transfer the selected teletext page into a display page buffer, adding extra data such as charac- ter set extension and non-spacing attributes. 3.5.1. memory manager the memory manager is the core of the internal tpu firmware. most of the acquisition and display related functions are controlled by this management. fig. 3 ? 3: memory manager dma interface 12k program rom 12k/24k character rom zero page stack page i/o page adr data be rdy 65c02 busreq display data adr extra page 8000 1000 0000 d000 display memory memory manager display controller page memory page table scratch memory acquisition
preliminary data sheet vct 38xxa/b micronas 51 3.5.2. memory organization the upper end of the memory is defined by the sram size, the lower end can be defined with the page_memory command. default memory organi- zation is shown in fig. 3 ? 4. fig. 3 ? 4: memory organization the memory organization depends on available sram size. if external sram is not available, there is only one display bank for osd and teletext and the page memory starts at a different location (see table 3 ? 1). 3.5.3. page table the memory management is based on a fixed size page table, which has entries for every hexadecimal page number from 100 to 8ff. the page table starts with page 800 and contains a 2-byte page pointer for every page. the page table can be read with the command read_page_info sending the page number and reading the 2-byte page pointer containing: ? sram pointer ? cycle flag ? memory flag ? subpage flag ? update flag ? protection flag the sram pointer gives the location where the page is stored in memory. the page size is fixed to 1 kbyte, only ghost rows are allocated dynamically. the cycle flag will be set as soon as this page is detected in the transmission cycle even if it cannot be stored in memory. only if the page is really stored in memory, the memory flag will be set. the subpage flag will be set for every page in cycle if the page subcode is different from 0000h or 3f7fh. the update flag is set every time a page is stored and will be reset only for the display page after updating the display mem- ory. a page with protection flag set will never be removed from memory. the memory manager uses page priorities to decide which pages should be stored or removed from mem- ory. if no more memory is available, pages with lowest priority are removed automatically and the higher prior- ity pages are stored at their place. by setting the page priority the programmer has control over the memory management. the page table is fully controlled by the memory man- ager and should never be written by external software. to change the page table flags the command change_page_info can be used. table 3 ? 1: memory organization memory segment address sram size 128k 19k 16k 3k display bank h ? 3000 h ? 4000 h ? 3000 h ? 0000 ttx bank h ? 2000 h ? 4000 h ? 3000 h ? 0000 page table h ? 0000 h ? 0000 h ? 0000 no acquisition scratch h ? 1000 h ? 1000 h ? 1000 no page memory h ? 4000 h ? 1800 h ? 1800 no 08 00 00 = 4mbit 02 00 00 = 1mbit 00 80 00 = 256kbit 00 40 00 00 30 00 00 20 00 00 10 00 00 00 00 4kbytes ttx display bank n x 1 kbyte page memory sram 4kbytes display bank 4kbytes page table 4kbytes acquisition scratch
vct 38xxa/b preliminary data sheet 52 micronas fig. 3 ? 5: page format table 3 ? 2: page table format index 2-byte page pointer 000 start magazine 8 001 ... 100 cycle flag memory flag subpage flag 11-bit sram pointer update flag protect flag ... 1f0 hexadecimal pages (e.g. top) ... 7fe 7ff end magazine 7 status language 12 ? 14 control 4 ? 11 subcode in subcode req priority subcode high subcode low index page mag 1 kbyte page data row flag 0 ? 7 row flag 8 ? 15 row flag 16 ? 23 row flag 24 ? 31 ghost row pointer subpage pointer 8 byte 8 byte packet x/01 packet x/24 packet x/00 24 byte
preliminary data sheet vct 38xxa/b micronas 53 3.5.4. ghost row organization page-related ghost rows are stored in blocks of 128 bytes. these ghost blocks are linked together using 2-byte ghost row pointers. the first pointer can be found in the basic page, all following pointers are part of the block header. a zero pointer indicates the end of the chain. fig. 3 ? 6: ghost row organization every ghost block contains 3 ghost rows which can be identified by 3 row identification bytes in the block header. the row identification contains designation code and row number. the row number is reduced to a 3-bit tag. all ghost rows in one block belong to the same page. if the memory manager removes a page from memory, the linked ghost blocks will also be removed. fig. 3 ? 7: ghost block structure ghost pointer page table page 100 page pointer ghost pointer ghost block 0000 ghost block table 3 ? 3: ghost row identification row number tag row 000 empty 001 row 25 010 row 26 011 row 27 100 row 28 101 row 29 110 row 30 111 row 31 3-bit row number 4-bit designation code ? aa ?? aa ?? aa ? row 2 row 1 row 3 ghost row pointer 40 byte row 1 data 40 byte row 2 data 40 byte row 3 data 8 byte block header
vct 38xxa/b preliminary data sheet 54 micronas 3.5.5. subpage manager any page in cycle can have a number of subpages, identified by subcode. in normal mode the subpage manager will acquire only one subpage of every requested page. this subpage can be any if subcode ffff is requested or it will be selected according to the requested subcode. after a page_request command with subcode f0xx, the subpage manager will acquire all subpages of the requested page. the subpages will be chained in the same order as they are transmitted, i.e. every new subcode will be added at the end of chain. the page table entry points to the subpage which was transmitted first after the page request. the read_page_info command will reply the page table pointer and the actual number of subpages in chain. after a page_request command with subcode f1xx, the subpage manager will acquire all subpages of the requested page but will allocate only a limited amount of memory to store these subpages. the parameter ? page subcode low ? will define the length (in number of subpages) of a ring buffer in page memory which will hold the recently received subpages. in this case, the read_page_info command will return an index pointing to the most recently updated subpage in chain, together with the subcode of this page. the display_page_request command searches and displays a page according to the requested dis- play subcode. the search starts from page table and continues through the subpage chain if there is any. a rolling header will be displayed if the requested sub- page cannot be found in memory. a requested display subcode ffff (don ? t care sub- code) will only search and display the first subpage in chain, thus there is no rolling subpage anymore. a display_page_request command with subcode f0xx (follow subcode) will search and display the last received subpage in chain, thus it is possible to request all subpages in background while still showing rolling subpages in display. fig. 3 ? 8: subpage organization page 100 subcode 0002 0000 page 100 subcode 0001 subpage pointer page 100 subcode 0003 subpage pointer page pointer page table
preliminary data sheet vct 38xxa/b micronas 55 3.6. wst display controller the display controller reads data from a display page buffer in the internal/external sram. the display page buffer is organized in rows which are separated into level 1 data such as character codes and spacing attributes and into level 2 data, such as character set extension and non-spacing attributes. to limit the memory amount for level 2 data, a slightly modified stack model is used, in which one pointer bit for every character location indicates the presence of additional parallel attributes. fig. 3 ? 9 shows the organization of the stack row buffer. in this stack model the number of non-spacing attributes per row is limited to 40, which agrees with the wst and cept specification. fig. 3 ? 9: stack row buffer the display controller includes two row buffers. the first row buffer holds a copy of a teletext row from the display page buffer. this decreases the data rate through the sram interface by a factor of 10 or 8, because new teletext row data is needed only after 10 lines in pal or 8 lines in ntsc mode. the second row buffer stores all display attributes in parallel, to allow level 2 display without additional decoding. to present a wst level 2 display, the teletext display controller has to evaluate the following attributes in parallel, that is for every character location: ? 10-bit character code ? 5-bit foreground color ? 5-bit background color ? 2-bit size ? 5-bit flash ? 1-bit invert ? 1-bit separated ? 1-bit conceal ? 1-bit underline ? 1-bit boxing/window additional attributes are defined to improve the display of caption and osd text: ? 1-bit italics ? 1-bit shadow ? 1-bit color mode the display controller delivers 5-bit digital color infor- mation, a shadow signal for contrast reduction, and a fast blank signal. the color bus is used to address the color look-up table (clut) in the video processor. by this means, the full level 2 color spectrum can be dis- played. level 2 buffer 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 pointer char 36 attr. char 38 char 40 char 39 char 36 char 37 level 1 buffer char 10 attr. char 1 char 2 char 3 char 4 char 5 char 6 char 7 char 8 char 9 char 10 char 3 attr. char 3 attr. char 3 attr. char 3 attr. char 6attr. char 6 attr. char 6 attr. char 10 attr. char 10 attr.
vct 38xxa/b preliminary data sheet 56 micronas 3.7. display memory the tpu supports a variable number of display memo- ries, each 4 kbytes large. one bank is used to store the display information of the selected teletext page. the bank location can be defined with the command display_ttx_pointer. other banks can be used to store any kind of display data in level 1 or level 2 for- mat. switching between these banks is fast and can be programmed with the command display_pointer. bank switching allows generation of osd menus with- out affecting the teletext display. fig. 3 ? 10: display memory organization (level 2) display bank 40 byte level 1 40 byte level 2 full row attr. 40-bit pointer 40 byte level 1 40 byte level 2 full row attr. 40-bit pointer 40 byte level 1 40 byte level 2 full row attr. 40-bit pointer 40 byte level 1 40 byte level 2 full row attr. 40-bit pointer 40 byte level 1 40 byte level 2 full row attr. 40-bit pointer 40 byte level 1 40 byte level 2 full row attr. 40-bit pointer ttx display bank row 0 row 0 row 1 row 1 row 46 row 25 sram autoincrement
preliminary data sheet vct 38xxa/b micronas 57 table 3 ? 5: full row attribute + 55h r/w full row attribute bit reset function 7 - 1 = row is displayed blank 0 = row is displayed using row data 6 - 1 = row is displayed in double height 0 = row is displayed in normal height 5 - 1 = row is displayed in level 2 mode 0 = row is displayed in level 1 mode 4 to 0 - 5-bit value defining full row background color table 3 ? 6: level 1 spacing attributes code function action notes 00 alpha black set alpha mode and foreground color of following alpha characters select character set 0 01 alpha red 02 alpha green 03 alpha yellow 04 alpha blue 05 alpha magenta 06 alpha cyan 07 alpha white 08 flash normal 09 flash off set at 0a boxing off set at double 0b boxing on set at double 0c size normal set at 0d size double height 0e size double width 0f size double 10 mosaic black set mosaic mode and foreground color of following mosaic characters select character set 1 11 mosaic red 12 mosaic green 13 mosaic yellow 14 mosaic blue 15 mosaic magenta 16 mosaic cyan 17 mosaic white 18 conceal set at 19 contiguous mosaic set at 1a separated mosaic set at 1b esc 1c black background set at 1d new background set at 1e hold mosaic set at 1f release mosaic shaded attributes are default at start of each display row. table 3 ? 7: level 2 parallel attributes 7 6 5 4 3 2 1 0 function p 0 0 color foreground color p 0 1 color background color p 1 0 flash flash mode p 1 1 0 0 l set character set p11010dhdwsize p110110uunderline/separated p110111i inverted p111000cconceal p111001wwindow/boxing p111010sshadow p111011ititalic p111100cmcolor mode table 3 ? 8: color look-up table 4 3 2 1 0 display color 00000black 00001red 00010green 00011yellow 00100blue 00101magenta 00110cyan 00111white 01000transparent 01001reduced red 01010reduced green 01011reduced yellow 01100reduced blue 01101reduced magenta 01110reduced cyan 01111reduced white 1xxxxprogrammable table 3 ? 4: flash modes 4 3 2 1 0 function 00000off 00001normal 00101normal fast phase 1 01001normal fast phase 2 01101normal fast phase 3 00010inverted 00110inverted fast phase 1 01010inverted fast phase 2 01110inverted fast phase 3 00011color table 00111color table phase 1 01011color table phase 2 01111color table phase 3 1 0 0 x x incremental 1 0 1 x x decremental
vct 38xxa/b preliminary data sheet 58 micronas 3.8. character generator characters are addressed using a 10-bit character code. the 2 msbs of the character code define 1 of 4 character sets. character set selection is done using level 2 parallel attributes (see table 3 ? 7 on page 57). each character set contains 224 characters. the first 32 characters in each character set are reserved for control codes (see table 3 ? 6 on page 57). on a single screen, 896 different characters can be displayed. characters can be displayed in several pixel resolu- tions provided that the according font is available. the character generator supports horizontal resolution of 8 or 10 pixel/char and vertical resolution of 8, 10, or 13 lines/char. characters can be combined without separating borders to create more complex character definitions (e.g. kanji or icons). the pixel clock can be either 10.125 mhz or 20.25 mhz. to get 10-bit pixel information from the character font, two memory cycles are needed. the character font is part of the mask-programmable rom, but supplied with its own bus structure (see fig. 3 ? 2 on page 50). by this means the data transfer between character rom and teletext display controller does not stop the cpu. both bus structures are connected via a memory inter- face which allows cross-connections using dma or wait cycles. if the character font size exceeds 12 kbytes, part of the character font can be shifted into the program rom which causes dma cycles. there- fore only less frequently used characters should be placed into the program rom. vice versa seldom used cpu code can be put into the character rom. the wst specification defines a number of 7-bit code tables, which are filled with 96 characters only (the msb is used for parity check). in the g0 code table some characters have several language dependent variations. additionally characters from the g0 code table can be combined with diacritical marks from the g2 code table (row 26). furthermore different code tables are defined for languages like cyrillic, greek or arabic. thus it is not possible to simply transform the code tables into a continuous character font rom without getting unused rom space and multiple defined character fonts. this problem is solved by implementing a character code mapping (see fig. 3 ? 11 on page 59). the 5 msbs of each character code are mapped into another 5-bit code which is then used to address the character font rom. by this means the whole charac- ter font is subdivided into 32 blocks of 32 characters which can freely be distributed over the 4 character sets. the character code mapping is implemented as ram and can be programmed by software. after reset the tpu initializes the mapping ram for standard wst latin code tables. the tv controller can select predefined mappings for latin, cyrillic and arabic teletext via the command display_mode (see table 3 ? 16 on page 72). the same command allows selection of a user defined mapping which has to programmed in advance using command user_mapping. table 3 ? 9: character resolutions matrix (h x v) char/sc reen (pal) char/sc reen (ntsc) osd width # char in 12k font # char in 24k font single character 8 x 8 40 x 32 40 x 28 32 s 1600 3072 10 x 8 40 x 32 40 x 28 40 s 1280 2458 8 x 10 40 x 26 40 x 22 32 s 1280 2458 10 x 10 40 x 26 40 x 22 40 s 1024 1966 8 x 13 40 x 20 40 x 17 32 s 800 1536 10 x 13 40 x 20 40 x 17 40 s 640 1229 combined character (2 x 2) 16 x 16 20 x 16 20 x 14 32 s 400 768 20 x 16 20 x 16 20 x 14 40 s 320 614 16 x 20 20 x 13 20 x 11 32 s 320 614 20 x 20 20 x 13 20 x 11 40 s 256 492 16 x 26 20 x 10 20 x 8.5 32 s 200 384 20 x 26 20 x 10 20 x 8.5 40 s 160 307 combined character (2 x 1) 16 x 10 20 x 26 20 x 22 32 s 640 1229 16 x 13 20 x 20 20 x 17 32 s 400 768 20 x 13 20 x 20 20 x 17 40 s 320 614 combined character (1x 2) 10 x 16 40 x 16 40 x 14 40 s 640 1229
preliminary data sheet vct 38xxa/b micronas 59 3.8.1. character code mapping fig. 3 ? 11: character code mapping character set 0 g2 national national national national national national national national 10-bit character code = 2-bit character set (level 2) + 8-bit character value (level 1) 000h 080h 100h 180h 200h 280h 300h g3 g3 g3 user user user user 380h mapping ram 32 x 5 bit g2 g2 g2 user user user user g1 g0 g1 user user user g3 g3 12800 byte character rom g2 g2 user g1 national g1 national national g0 g0 g0 national g0 g0 g0 block of 32 char g3 greek greek cyrillic cyrillic cyrillic hebrew arabic arabic arabic 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 character set 1 character set 2 character set 3 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 font pointer farsi
vct 38xxa/b preliminary data sheet 60 micronas 3.8.2. character font rom the character font rom is mask-programmable. design of customer specific characters (user font) is supported by a windows ? based pc tool named mofa (micronas osd and font assembler). in combi- nation with the vct 38xxa/b emulator board it is pos- sible to download character fonts and verify them on the tv screen. fig. 3 ? 12: character font rom for teletext
preliminary data sheet vct 38xxa/b micronas 61 3.8.3. latin font mapping fig. 3 ? 13: latin font mapping
vct 38xxa/b preliminary data sheet 62 micronas 3.8.4. cyrillic font mapping fig. 3 ? 14: cyrillic font mapping
preliminary data sheet vct 38xxa/b micronas 63 3.8.5. arabic font mapping fig. 3 ? 15: arabic font mapping
vct 38xxa/b preliminary data sheet 64 micronas 3.8.6. closed caption font (on vct 38xxb only!) fig. 3 ? 16: character font rom for closed caption fig. 3 ? 17: closed caption font mapping
preliminary data sheet vct 38xxa/b micronas 65 3.8.7. character font structure fig. 3 ? 18: font structure 10 x 10 fig. 3 ? 19: font structure 8 x 13 line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8 line 9 line 10 line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8 line 9 line 10 line 1 line 2 line 3 line 4 ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? a ? ? a ? ? a ? ? a ? character font ? a ? ? a ? ? a ? ? a ? ? a ? ? a ? ? a ? ? a ? ? a ? ? a ? ? e ? ? e ? ? e ? ? e ? ? b ? ? b ? ? b ? ? b ? ? b ? ? b ? ? b ? ? b ? ? b ? ? b ? ? f ? ? f ? ? f ? ? f ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? @ ? ? d ? ? d ? ? d ? ? d ? ? c ? ? c ? ? c ? ? c ? ? c ? ? c ? ? c ? ? c ? ? c ? ? c ? ? g ? ? g ? ? g ? ? g ? extension font line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8 line 9 line 10 line 1 line 2 line 3 line 4 lsb msb 0 9 line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8 line 9 line 10 line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8 line 9 line 10 line 11 line 12 line 13 line 14 ? p ? ? p ? ? p ? ? p ? ? p ? ? p ? ? p ? ? p ? ? p ? ? p ? ? q ? ? q ? ? q ? character font lsb msb 0 7 line 11 line 12 line 13 line 15 line 16 line 1 line 2 line 3 ? p ? ? p ? ? p ?
vct 38xxa/b preliminary data sheet 66 micronas 3.9. national character mapping table 3 ? 10: character set options option bits c14,c13,c12 character set 6 38 40 55 70 128 000 english polish english (us) english english (us) programmable 001 french french french french slovakian programmable 010 swedish swedish swedish swedish hungarian programmable 011 czech czech czech turkish serbian programmable 100 german german german german albanian programmable 101 spanish serbian spanish spanish polish programmable 110 italian italian italian italian turkish programmable 111 estonian estonian estonian estonian rumanian programmable table 3 ? 11: language codes code language 0 english 1 french 2 swedish, finnish 3 czech 4 german 5 spanish 6 italian 7 estonian, finnish 8 english (us) 9 slovakian 10 hungarian 11 serbian, croatian, slovene 12 albanian 13 polish 14 turkish 15 rumanian 16 cyrillic (russian, bulgarian) 17 greek 18 cyrillic (serbian, montenegro) 19 yu latin 20 arabic 21 hebrew 22 farsi 23 lettish, lithuanian 24 cyrillic (ukrainian) 25 ? 255 not defined
preliminary data sheet vct 38xxa/b micronas 67 table 3 ? 12: national option mapping language g0/g1 table position 2/3 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13 7/14 albanian 5/15 2/4 13/12 13/2 12/12 12/3 11/12 9/1 13/13 13/3 12/13 13/1 11/13 czech 5/15 12/9 13/13 10/11 12/13 12/11 8/4 15/13 9/3 8/3 12/0 9/2 11/13 english 2/3 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13 7/14 english (us) 5/15 2/4 4/0 14/4 13/5 15/4 14/6 13/0 14/7 14/5 15/6 15/5 15/7 estonian, finnish 5/15 11/11 11/12 8/13 8/14 12/12 8/15 11/10 11/13 8/10 8/11 12/13 8/12 french 9/3 8/1 8/5 9/1 9/7 8/2 8/8 5/15 9/5 8/7 9/8 8/9 9/0 german 5/15 2/4 15/0 8/13 8/14 8/15 14/6 13/0 14/0 8/10 8/11 8/12 9/10 hungarian 5/15 9/2 9/14 8/4 8/14 10/1 12/15 11/15 9/3 9/4 8/11 8/3 8/12 italian 2/3 2/4 9/3 14/0 9/0 5/13 5/14 5/15 8/2 8/5 9/6 9/5 8/6 polish 5/15 14/3 13/15 13/8 12/7 15/8 13/3 9/4 10/9 13/9 13/7 15/9 13/11 rumanian 5/15 14/1 10/14 10/5 14/14 14/11 10/6 15/1 10/15 8/7 14/15 12/5 8/8 serbian, croatian 5/15 2/4 13/12 13/2 12/12 12/3 11/12 13/0 13/13 13/3 12/13 13/1 11/13 slovakian 5/15 12/9 13/13 10/11 12/13 12/11 8/4 15/13 9/3 8/3 12/0 9/2 11/13 spanish 9/0 2/4 9/15 8/3 9/3 8/4 9/4 9/2 9/9 8/12 9/11 9/5 8/5 swedish, finnish 5/15 14/1 9/14 8/13 8/14 9/13 8/15 13/0 9/3 8/10 8/11 9/12 8/12 turkish 13/6 10/13 10/8 14/14 8/14 8/0 8/15 10/12 15/1 14/15 8/11 9/0 8/12 yu latin 5/15 2/4 13/12 13/2 12/12 12/3 11/12 13/0 13/13 13/3 12/13 13/1 11/13
vct 38xxa/b preliminary data sheet 68 micronas 3.10. four-color mode in ? four-color mode ? the color depth of single or multi- ple characters can be increased to 4 colors (e.g. to dis- play icons or 3-d effects). a special font organization is required because two consecutive characters will be combined. the number of 4-colored characters is only limited by font size. the ? four-color mode ? is controlled via the level 2 par- allel attribute ? color mode ? . setting the bit cm to 1 activates the ? four-color mode ? until the end of row or until the bit cm is set to 0 again. at the start of each display row the ? four-color mode ? is disabled. a character with active ? four-color mode ? attribute will be combined with its font neighbor to define a 2 bit/pixel character matrix. the 2 additional colors are derived from the active foreground and background colors by inverting bit 3 of the color code. using the programmable part of the clut it is possible to display characters in 4 out of 4096 colors. if the ? four-color mode ? attribute is set for a character with even character code n, this character is combined with its font neighbor addressed by code n + 1. if the ? four-color mode ? attribute is set for a character with odd character code, this character is combined with itself. the neighbor character does not change the definition of foreground and background pixel which is used to control flash and mix mode. fig. 3 ? 20: four-color mode table 3 ? 13: color allocation pixel definition color allocation character n character n+1 0 0 background 1 0 foreground 0 1 background .xor. 8 1 1 foreground .xor. 8 matrix of character n matrix of character n+1 4 color display + = 00 10 01 11
preliminary data sheet vct 38xxa/b micronas 69 3.11. osd layer apart from the wst layer, there is an additional osd layer on chip. the osd layer accesses the cpu mem- ory via dma to read text, display attributes, and char- acter font information. the color outputs of the osd layer can have higher priority than the wst layer out- puts. thus, it is possible to overlay the teletext display with an additional layer for user guidance (see fig. 3 ? 21). fig. 3 ? 21: display layer the osd layer reads text strings addressed by a pro- grammable text pointer. codes smaller than 80h will address the character font, codes greater or equal 80h are interpreted as control codes to change color or character set (see table 3 ? 14). after reading a control code the osd layer will do an additional read to get the next character code. osd layer wst layer full screen layer table 3 ? 14: osd layer control codes code function notes 01 underline on only for 13 scanlines/character 02 underline off 03 flash on 04 flash off 05 italics on 06 italics off 07 transparent layer becomes transparent 08 shadow layer becomes transparent and contrast is reduced to 66% 0c end end of layer 0d cr end of text line 0e ? 7f ascii character using font 1 or font 2 80 ? ff control code only one control code per character is allowed. depending on osd mode, the control code defines either color or character set. color bit 0 = foreground color blue bit 1 = foreground color green bit 2 = foreground color red bit 3 = background color blue bit 4 = background color green bit 5 = background color red bit 6 = replace white by transparent bit 7 = 1 character set bit 0 = bit 7 of character code bit 1 = bit 8 of character code bit 2 = bit 9 of character code bit 3 = bit 4 = bit 5 = bit 6 = latching shift to character set bit 7 = 1 shaded attributes are default at start of each text line.
vct 38xxa/b preliminary data sheet 70 micronas 3.12. command language the tpu supports a command language, allowing the tv controller to start complex processing inside the tpu with simple commands. the tv controller is not burdened with time consuming tasks like page search- ing or data shuffling. table 3 ? 15 lists all available commands. for a more detailed description of the command language see table 3 ? 16. the application software has to send commands to the tpu via i 2 c bus using the command subaddress sub4 (see section 3.14.1.3. on page 86). table 3 ? 15: command language cross reference code dec. code hex. command name no. write parameter no. read parameter status register 0 00 dummy 0 0 x000 0000 1 01 reset 0 0 x000 0000 2 02 escape 0 0 x000 0000 3 03 version 0 2 x000 0000 4 04 test 0 0 x000 0000 5 05 test 0 0 x000 0000 6 06 dram mode 3 0 x000 0000 7 07 acquisition mode 6 2 x000 0000 8 08 display mode 3 0 x000 0000 9 09 display ttx pointer 2 0 x000 0000 10 0a display pointer 3 0 x000 0000 11 0b display clear 2 0 x000 0000 12 0c page request 8 3 x0x0 0000 13 0d display time pointer 2 0 x000 0000 14 0e read dram size 0 3 x000 0000 15 0f read vps 0 15 x0x0 0000 16 10 read quality 0 6 x000 0000 17 11 read display mode 0 3 x000 0000 18 12 read reset source 0 1 x000 0000 19 13 read rolling header 0 24 x000 0000 20 14 read page info 2 7 x000 0000 21 15 read page row 5 40 x0x0 0000 22 16 change page info 3 0 x000 0000 23 17 search mpet 0 1 + (n*4) x0x0 0000 24 18 read display page 0 4 x000 0000 25 19 page memory 2 0 x000 0000 26 1a display page request 5 0 x000 0000 27 1b page table reset 0 0 x000 0000 28 1c search next page 3 6 x0x0 0000 29 1d read page cycle 0 9 x000 0000 30 1e read top code 2 2 x000 0000 31 1f read rolling time 0 8 x000 0000 32 20 copy page row 8 0 x0x0 0000 33 21 copy data 7 0 x000 0000 34 22 search next top code 3 4 x0x0 0000 35 23 read ghost row 6 40 x0x0 0000
preliminary data sheet vct 38xxa/b micronas 71 36 24 read 8/30 row 1 40 x0x0 0000 37 25 read priority 0 5 x000 0000 38 26 page priority 2 0 x000 0000 39 27 search ait 0 1 + (n*4) x0x0 0000 40 28 read top status 0 2 x000 0000 41 29 search ait title 2 17 x0x0 0000 42 2a reset ghost row status 0 0 x000 0000 43 2b search mpt 0 1 + (n*4) x0x0 0000 44 2c copy ait title 5 17 x0x0 0000 45 2d search direct choice 1 1 + (n*2) x0x0 0000 46 2e read hamming 1 1 x000 0000 47 2f read hamming 2 3 3 x000 0000 48 30 display column 3+length 0 x000 0000 49 31 display fill 4 0 x000 0000 50 32 read bttl 0 9 x0x0 0000 51 33 read next page 2 2 x000 0000 52 34 change btt magazine 1 0 x000 0000 53 35 read wss 0 15 x0x0 0000 54 36 read caption 1 0 7 x0x0 0000 55 37 read caption 2 0 7 x0x0 0000 56 38 display font pointer 5/1/3 0 x000 0000 57 39 display read column 3 length x000 0000 58 3a user character set 8 0 x000 0000 59 3b user esc character set 8 0 x000 0000 60 3c full row attribute 3 0 x000 0000 61 3d user mapping 32 0 x000 0000 62 3e execute code on stack 0 0 x000 0000 63 3f disable ghost rows 1 0 x000 0000 table 3 ? 15: command language cross reference, continued code dec. code hex. command name no. write parameter no. read parameter status register
vct 38xxa/b preliminary data sheet 72 micronas note: if not otherwise designated, all parameters in the following table are specified as single bytes. as write parameter magazine numbers 8 and 0 have the same meaning, as read parameter the magazine number is a true 4-bit number (e.g. magazine 8= 00001000). for write parameters the values in parentheses indicate default values after reset (in hex notation). for compatibility reasons every undefined bit in a write parame- ter should be set to ? 0 ? . undefined bits in a read parameter should be treated as ? don ? t care ? . table 3 ? 16: command language code function write parameter read parameter notes operational & test commands 00 dummy no action 01 reset software reset of 65c02 02 escape escape to other codes 03 version cpu pointer high cpu pointer low show version in osd layer cpu pointer to text in rom 04 test reserved for testing 05 test reserved for testing 06 dram mode dram mode (06) flash inc (05) control enable (ff) dram mode = i/o page register 028eh flash freq = flash inc / (256 * 0.00324) control enable: bit0 = c4 erase page bit1 = c5 news flash bit2 = c6 subtitle bit3 = c7 suppress header bit4 = c8 update indicator bit5 = c9 interrupted sequence bit6 = c10 inhibit display bit7 = c11 magazine parallel 07 acquisition mode acquisition mode (00) init subcode high (ff) init subcode low (ff) gain max (1f) filter max (1f) acq. sync slicer (19) gain filter acquisition mode: bit0 = no slicer adaption bit1 = no bit error in framing code bit2 = limit slicer adaption bit3 = acq. sync slicer init subcode: automatic subcode request after page table reset gain max: only used if bit2 = 1 filter max: only used if bit2 = 1 acq. sync slicer: only used if bit3 = 1 62 execute code on stack execute ? jsr 0x100 ? memory management commands 14 read dram size dram size high dram size low dram mode dram size: 000ch = 3 kbyte sram 004ch = 19 kbyte sram 0200h = 128 kbyte sram 0240h = 144 kbyte sram 0400h = 256 kbyte sram 0800h = 512 kbyte sram dram mode: see i/o page register 028eh 25 page memory dram bank (00) dram high (40) start of page memory execute page table reset 27 page table reset reset page table reset ghost row status reset data service status reset cycle count reset memory count reset ghost count reset priorities clear rolling header clear vps data clear wss data
preliminary data sheet vct 38xxa/b micronas 73 42 reset ghost row status ghost row status: bit0 = row 24 in cycle bit1 = row 25 in cycle bit2 = row 26 in cycle bit3 = row 27 in cycle bit4 = row 28 in cycle bit5 = row 29 in cycle bit6 = row 30 in cycle bit7 = row 31 in cycle 63 disable ghost rows ghost row disable ghost row disable: bit0 = disable row 24 acquisition bit1 = disable row 25 acquisition bit2 = disable row 26 acquisition bit3 = disable row 27 acquisition bit4 = disable row 28 acquisition bit5 = disable row 29 acquisition bit6 = disable row 30 acquisition bit7 = disable row 31 acquisition 29 read page cycle ghost row status 2 byte cycle count 2 byte memory count 2 byte ghost count data service status memory status = number of pages in cycle = number of pages in memory = number of ghost blocks in memory data service status: bit0 = 8/30 format 1 updated bit1 = 8/30 format 2 updated bit2 = vps updated bit3 = wss updated bit4 = caption 1st field updated bit5 = caption 2nd field updated memory status: bit0 = memory full 38 page priority enable (00) border (ff) enable: bit0 = enable priority manager border: min/max border for page priorities 37 read priority highest priority lowest priority border priority magazine number page number = max priority in page memory = min priority in page memory = min/max border for page priorities = page with lowest priority page related commands 12 page request magazine number page number page subcode high page subcode low priority quantity start magazine number start page number number of open requests removed magazine number removed page number remove pages from memory beginning at start page if page priority is disabled, ignores start page if page priority is enabled magazine number: bit0 ? 3 = magazine number bit4 = not used bit5 = hex request bit6 = backward request bit7 = forced request = ignore cycle flag 20 read page info magazine number page number page pointer high page pointer low subpage count ghost row count ring buffer index page subcode high page subcode low = pointer from page table = number of subpages in chain = number of ghost rows in chain if page request with subcode f1xx 22 change page info magazine number page number page table flags page table flags: bit0 = protection bit1 = update bit2 = not used bit3 = not used bit4 = not used bit5 = subpage bit6 = memory bit7 = cycle table 3 ? 16: command language, continued code function write parameter read parameter notes
vct 38xxa/b preliminary data sheet 74 micronas 28 search next page magazine number page number search code magazine number page number page pointer high page pointer low subpage count ghost row count search in page table for cycle flag magazine number: bit0 ? 3 = magazine number bit4 = take search code bit5 = hex search bit6 = backward search bit7 = include start page search code: bit0 = search protection flag bit1 = search update flag bit2 ? 4 = not used bit5 = search subpage flag bit6 = search memory flag bit7 = search cycle flag 51 read next page magazine number page number magazine number page number calculate next page number magazine number: bit0 ? 3 = magazine number bit4 = not used bit5 = hex calculation bit6 = backward calculation bit7 = not used 21 read page row magazine number page number subpage number high subpage number low row number 40 byte row data row 0 ? 24 32 copy page row magazine number page number subpage number high subpage number low row number destination dram bank destination dram high destination dram low copy 40byte text row from page memory into dram 35 read ghost row magazine number page number subpage number high subpage number low row number designation code 40 byte row data row 25 ? 28 top commands 40 read top status top status 1 top status 2 top status 1: bit0 = not used bit1 = mpt link in plt bit2 = mpet link in plt bit3 = ait link in plt bit4 = btt in memory bit5 = mpt in memory bit6 = mpet in memory bit7 = ait in memory top status 2: bit0 ? 5 = not used bit6 = all mpet in memory bit7 = all ait in memory 30 read top code magazine number page number btt code mpt code code: bit0 ? 3 = data bit6 = hamming error 50 read bttl bttl error 8 byte bttl data bttl error: bit6 = hamming error in bttl bttl data: bit0 ? 3 = data bit6 = hamming error 52 change btt magazine magazine number (01) all top commands then refer to this magazine 43 search mpt number of mpts magazine number page number subpage number high subpage number low ... search in plt table 3 ? 16: command language, continued code function write parameter read parameter notes
preliminary data sheet vct 38xxa/b micronas 75 23 search mpet number of mpets magazine number page number subpage number high subpage number low ... search in plt 39 search ait number of aits magazine number page number subpage number high subpage number low ... search in plt 41 search ait title magazine number page number 5 byte data 12 byte title search in ait magazine number: bit0 ? 3 = magazine number (0#8) bit4 ? 6 = not used bit7 = ignore title language data: bit0 ? 3 = data bit6 = hamming error 44 copy ait title magazine number page number destination dram bank destination dram high destination dram low 5 byte data 12 byte title search in ait and copy title into dram magazine number: bit0 ? 3 = magazine number (0#8) bit4 ? 6 = not used bit7 = ignore title language data: bit0 ? 3 = data bit6 = hamming error 34 search next top code magazine number page number code condition magazine number page number code code flag search in btt magazine number: bit0 ? 3 = magazine number bit4 ? 5 = not used bit6 = backward search bit7 = include start page code condition: low nibble = btt code high nibble = search condition 0 = btt code in low nibble 1 = btt code # 0 2 = block page 3 = group page 4 = normal page 5 = subtitle page 6 = tv page 7 = block/tv page 8 = group/block/tv page 9 = subpage a = block/tv subpage b = group/block/tv subpage c = title page d = future page e = future page f = future page code: bit0 ? 3 = btt code bit6 = hamming error code flag: bit0 = subtitle page found bit1 = tv page found bit2 = block page found bit3 = group page found bit4 = normal page found bit5 = future page found bit6 = title page found bit7 = subpage found 45 search direct choice direct choice code number of ait entries magazine number page number ... search in ait table 3 ? 16: command language, continued code function write parameter read parameter notes
vct 38xxa/b preliminary data sheet 76 micronas miscellaneous data commands 36 read 8/30 row designation code 40 byte row data only format 1 and 2 are supported 1st byte of row data is already hamming decoded 15 read vps framing code counter 13 byte vps data = 51h = incremented every vps reception = biphase decoded vps bytes 3 ? 15 53 read wss framing code counter 13 byte wss data = 78h = incremented every wss reception = 102 wss elements from group 1 on 54 read caption 1 counter 6 byte caption data = incremented every reception in field 1 = 3x oversampling 55 read caption 2 counter 6 byte caption data = incremented every reception in field 2 = 3x oversampling 19 read rolling header 24 byte rolling header every row 0 in cycle 31 read rolling time 8 byte rolling time using time pointer 16 read quality text lines hamming errors parity errors soft errors io_acq_hsync_counter io_acq_sync_status updated every vbi 18 read reset source reset source reset source: bit0 = clock supervision bit1 = voltage supervision bit2 = watchdog all bits in reset source are reset after read 46 read hamming hamming (8,4) byte data hamming byte: bit0 ? 3 = data bit6 = hamming error 47 read hamming 2 hamming (24,18) 1st byte hamming (24,18) 2nd byte hamming (24,18) 3rd byte address mode data address: bit0 ? 5 = address bit7 = hamming error mode: bit0 ? 4 = mode data: bit0 ? 6 = data 33 copy data source dram bank source dram high source dram low length destination dram bank destination dram high destination dram low copy data from dram to dram display commands 17 read display mode display mode character set font mapping display mode: bit0 = forced boxing bit1 = reveal bit2 = box bit3 = time hold bit4 = page hold bit5 = row 24 hold bit6 = row 25 hold bit7 = row 26 hold 08 display mode display mode (18) character set (06) font mapping (00) display mode: see above character set: 6,38,40,55,70,128 font mapping: 0=latin 1=cyrillic/greek 2=arabic/farsi/hebrew 128=user defined 09 display ttx pointer dram high (20) dram low (00) page memory is copied to ttx pointer 10 display pointer dram high (20) dram low (00) scroll counter (00) display starts at pointer using scroll counter as line offset table 3 ? 16: command language, continued code function write parameter read parameter notes
preliminary data sheet vct 38xxa/b micronas 77 11 display clear dram high dram low clear display bank beginning at pointer (26 rows * 86 bytes) 13 display time pointer dram high (20) dram low (20) 8 byte time string from packet x/00 is copied to time pointer 26 display page request magazine number page number subpage number high subpage number low display delay (1e) magazine number: bit0 ? 3 = magazine number bit4 = change display delay bit5 = display clear (on update) bit6 ? 7 = not used subpage number: f0xx for rolling subpages display delay: delay after row 0 reception in steps of 3.24ms (255 = no update) only used if bit4 = 1 24 read display page magazine number page number subpage number high subpage number low current page in display 48 display column dram high dram low length byte list ... write to dram with increment of 86 bytes = number of bytes in list 49 display fill dram high dram low length character repeated write of 1 character to dram = number of repeated writes 56 display font pointer font mode (00) for font mode=1 or 2: font pointer high font pointer low extension font pointer high extension font pointer low font mode: 1 = write osd font 2 pointer 2 = write wst font 1 pointer for font mode=0 font mode: 0 = reset osd font 2 pointer osd font pointer = wst font pointer for font mode=3 or 4: display mode 1 display mode 2 font mode: 3 = select vctb 10x13 font 4 = select vctb 10x10 font 57 display read column dram high dram low length byte list ... read from dram with increment of 86 bytes = number of bytes to read 58 user character set language 000 (00) language 001 (01) language 010 (02) language 011 (03) language 100 (04) language 101 (05) language 110 (06) language 111 (07) if character set 128 is selected via command 08 ? display mode ? , these 8 languages will be selected by option bits c14,c13,c12 when esc code is inactive. 59 user esc character set esc language 000 (00) esc language 001 (00) esc language 010 (00) esc language 011 (00) esc language 100 (00) esc language 101 (00) esc language 110 (00) esc language 111 (00) if character set 128 is selected via command 08 ? display mode ? , these 8 languages will be selected by option bits c14,c13,c12 when esc code is active. 60 full row attribute full row attribute number of rows start row set full row attribute of specified rows without changing level 2 bit 61 user mapping 32 byte mapping data 32 bytes are copied into mapping ram via i/o page register 0276h table 3 ? 16: command language, continued code function write parameter read parameter notes
vct 38xxa/b preliminary data sheet 78 micronas 3.13. i/o register most hardware-related functions of the tpu are con- trolled by memory mapped i/o of the 65c02. the application software has access to the i/o registers via i 2 c bus using the cpu subaddresses sub1 and sub2 (see section 3.14.1.1. on page 86). most of the i/o registers can only be written and will not return useful data when read by application soft- ware. reset values are written by tpu during initializa- tion. note: for compatibility reasons, every undefined bit of a write register should be set to ? 0 ? . undefined bits of a read register should be treated as ? don ? t care ? . 0200 h r/w control register bit reset write function read function all 00 h during reset the control register is loaded with the contents of the address fff9h, but it can be read and written via software. 7 0 1 = cpu disable 0 = cpu enable 6 0 1 = program ram disable 0 = program ram enable 5 0 1 = program rom disable 0 = program rom enable 4 0 1 = character rom disable 0 = character rom enable 3 0 1 = dma interface disable 0 = dma interface enable 2 0 1 = i/o page disable 0 = i/o page enable 1 0 1 = test mode on 0 = test mode off 0 0 1 = burn-in test mode (only if test pin high) 0 = normal test mode 1 = burn-in test mode 0 = normal test mode 0202 h write standby bit reset function 2 0 1 = digital circuitry power off(cpu still active with slow clock) 0 = digital circuitry power on 0213 h write interface mode bit reset function 1 0 1 = standby enable (if bit 2 of register 0202h = 1) 0 = standby disable 0251 h write blanking stop bit reset function all 07 h horizontal stop of blanking pulse in character increments correct blanking pulse cannot be guaranteed if blanking start = blanking stop 0252 h write blanking start bit reset function all 00 h horizontal start of blanking pulse or self-timed hsync in character increments correct blanking pulse cannot be guaranteed if blanking start = blanking stop
preliminary data sheet vct 38xxa/b micronas 79 0254 h write display mode 1 bit reset function 7 0 1 = osd layer always uses font 1 0 = osd layer changes from font 1 to font 2 if ascii 20h 6 1 1 = enable osd layer 0 = disable osd layer 5 1 1 = active flash phase of osd layer 0 = inactive flash phase of osd layer 4 0 1 = 13 scanlines/character 0 = 8 scanlines/character 3 to 0 0 with this scan line the osd layer starts display of the first text line. by slow incrementing of this value soft scroll begins. 0255 h write display mode 2 bit reset function 7 0 1 = osd layer control code defines character set 0 = osd layer control code defines color 3 1 1 = 10.125mhz display clock 0 = 20.25mhz display clock 2 1 1 = font pointer offset 10 scanlines/character 0 = font pointer offset 8 or 16 scanlines/character (depending on bit 1) 1 0 1 = font pointer offset 16 scanlines/character 0 = font pointer offset 8 scanlines/character 0 1 1 = 10 scanlines/character 0 = 8 or 13 scanlines/character (depending on bit 4 in register 0254 h) 025a h write prio mode bit reset function 5 to 3 110 prio code for shadow pixel 2 to 0 101 prio code for normal pixel 025b h r/w fb mode bit reset write function read function all 00 h every read resets status 7 0 color bit 4(color output of osd layer) 6 0 color bit 3(color output of osd layer) 4 0 1 = inverted color output 0 = normal color output 0260 h write osd layer vertical start bit reset function all 00 h 60 h 9-bit value defining vertical position (in scanline) 1st write: bit 0 = msb 2nd write: bit 7 to 0 = 8 lsbs
vct 38xxa/b preliminary data sheet 80 micronas 0261 h write osd layer vertical stop bit reset function all 01 h 28 h 9-bit value defining vertical position (in scanline) 1st write: bit 0 = msb 2nd write: bit 7 to 0 = 8 lsbs 0262 h write osd layer horizontal start bit reset function all 16 h 8-bit value defining horizontal start position (in character) 0264 h write osd layer textpointer bit reset function all ? 16-bit value defining memory address of text 1st write: bit 7 to 0 = 8 msbs 2nd write: bit 7 to 0 = 8 lsbs 0265 h write osd layer 2nd color start bit reset function all 01 h 38 h 9-bit value defining vertical start for 2nd color (in scanline) 1st write: bit 0 = msb 2nd write: bit 7 to 0 = 8 lsbs 0266 h write osd layer 2nd color bit reset function 6 to 0 0c h 7-bit value defining 2nd color 2nd color is used during 1 text row (8, 10 or 13 scanlines) after 2nd color start 0267 h write wst layer vertical start bit reset function all 00 h 24 h 9-bit value defining vertical position (in scanline) 1st write: bit 0 = msb 2nd write: bit 7 to 0 = 8 lsbs 0268 h write wst layer horizontal start bit reset function all 0f h 8-bit value defining horizontal start position (in character) 026a h write wst layer vertical stop bit reset function all 01 h 28 h 9-bit value defining vertical position (in scanline) 1st write: bit 0 = msb 2nd write: bit 7 to 0 = 8 lsbs
preliminary data sheet vct 38xxa/b micronas 81 026b h write wst layer last row bit reset function all 01 h 1e h 9-bit value defining last scanline of the last row to display level 1 double height after this scanline the level 1 double height attribute will not be decoded anymore 1st write: bit 0 = msb 2nd write: bit 7 to 0 = 8 lsbs 026c h write rgb mode bit reset function 5 0 1 = wst layer mixed mode 0 = wst layer normal mode 4 to 3 0 11 = wst layer top 10 = wst layer opaque bottom 01 = wst layer transparent bottom 00 = wst layer disable 2 0 1 = osd layer mixed mode 0 = osd layer normal mode 1 to 0 0 11 = osd layer top 10 = osd layer opaque bottom 01 = osd layer transparent bottom 00 = osd layer disable 026d h write sync mode bit reset function 5 0 1 = double scan enable 0 = double scan disable 4 0 1 = blanking disable 0 = blanking enable 026f h write display mode 3 bit reset function 7 1 1 = 10 pixel/character 0 = 8 pixel/character 6 0 1 = double dot size in vertical direction(osd layer only) 0 = normal dot size in vertical direction 5 0 1 = double dot size in horizontal direction(osd layer only) 0 = normal dot size in horizontal direction 4 0 1 = black colors replaced by transparent & shadow(osd layer only) 0 = black colors displayed black 3 to 0 f h 4-bit value defining delay of horizontal start for both layers (in pixel) delay = mod 16 (character_width ? 2 ? value)(leftmost position should not be used!) 0270 h write display mode 4 bit reset function 4 0 1 = new mosaic mode (single switch to character set 1) 0 = old mosaic mode (static switch to character set 1) 3 0 1 = level 1 display mode (read 40 byte from display bank) 0 = level 2 display mode (read 86 byte from display bank) 2 0 1 = boxing enable 0 = boxing disable
vct 38xxa/b preliminary data sheet 82 micronas 1 0 1 = reveal enable 0 = reveal disable 0 0 this bit is taken as flash clock for the wst layer, the frequency should be around 6 hz. 0270 h write display mode 4 0273 h write display mode 5 bit reset function 4 0 wst layer scan line counter preset (lsb for zoom mode) 3 to 0 0 wst layer scan line counter preset 028e h write dram mode bit reset function 4 0 1 = next cpu write without weq but with address increment 0 = normal cpu write mode 3 0 1 = reset address pointer and switch off refresh during standbyt 0 = keep address pointer and refresh during standby 2 1 1 = display channel enable 0 = display channel disable 1 1 1 = slicer channel enable 0 = slicer channel disable 0291 h write acq ttx bitslicer frequency low bit reset function all - 8 lsbs of bitslicer frequency 0292 h write acq ttx bitslicer frequency high bit reset function 3 1 1 = phinc enable phase inc = freq*(1 + 1/8) before framing code phase inc = freq*(1 + 1/16) after framing code 0 = phinc disable phase inc = freq 2 to 0 - 3 msbs of bitslicer frequency freq = 2 11 * bitfreq / 20.25mhz = 702 for pal = 579 for ntsc 0293 h write acq vps bitslicer frequency low bit reset function all - 8 lsbs of bitslicer frequency 0294 h write acq vps bitslicer frequency high bit reset function 3 1 1 = phinc enable phase inc = freq*(1 + 1/8) before framing code phase inc = freq*(1 + 1/16) after framing code 0 = phinc disable phase inc = freq 2 to 0 - 3 msbs of bitslicer frequency freq = 2 11 * bitfreq / 20.25mhz = 506 for vps or wss = 153 for caption
preliminary data sheet vct 38xxa/b micronas 83 029c h read acq soft error counter bit reset function 5 to 0 ? 6-bit soft error counter counts number of soft error corrected bytes counter stops at 63 reset after read 029e h read acq sync status bit reset function 7 ? 1 = field 1 set at line 624 (pal) or line 524 (ntsc) 0 = field 2 reset at line 313 (pal) or line 263 (ntsc) 6 ? 1 = vertical retrace set at line 628 (pal) or line 528 (ntsc) 0 = vertical window reset at line 624 (pal) or line 524 (ntsc) 029f h write acq standard bit reset function 7 0 1 = caption enable in field 2 0 = caption disable in field 2 6 0 1 = caption enable in field 1 0 = caption disable in field 1 5 0 1 = vps enable 0 = vps disable 7 to 5 0 vps and caption cannot be used at the same time, therefore these combinations are used to enable wss reception on a pal+ signal 0 = 1 = vps 2 = caption field 1 3 = wss & vps 4 = caption field 2 5 = wss & vps 6 = caption field 1&2 7 = wss 4 1 1 = acquisition enable 0 = acquisition disable 1 to 0 0 00 = pal mode 10 = ntsc mode 11 = caption full field mode
vct 38xxa/b preliminary data sheet 84 micronas 02a3 h write acq video input bit reset function 2 to 0 0 000 = vin1 001 = vin2 010 = vin3 011 = vin4 100 = vin5 02a4 h read acq hsync counter bit reset function 7 to 0 0 number of detected horizontal sync pulses per frame divided by 4 sync pulse is detected if within horizontal window of hpll counter is latched with vertical sync, the register can be read at any time
preliminary data sheet vct 38xxa/b micronas 85 3.14. i 2 c-bus slave interface communication between the tpu and the tv control- ler is done via i 2 c bus. for detailed information on the i 2 c bus please refer to the philips manual ? i 2 c bus specification ? . the tpu acts as a slave transmitter/receiver and uses clock synchronization to slow down the data transfer if necessary. general call address will not be acknowl- edged. different memories and functions of tpu can be accessed by subaddressing. the byte following the slave address byte is defined as the subaddress byte. maximum length of an i 2 c telegram is 256 bytes fol- lowing slave address and subaddress byte. the inter- face supports data transfer with autoincrement. the i 2 c bus interface is interrupt-driven and uses an internal 48-byte buffer to collect i 2 c data in real-time without disturbing internal processes. this is done to avoid clock synchronization as far as possible. when the tpu has to process the i 2 c buffer and the i 2 c tele- gram has not yet been stopped, the i 2 c clock line will be held down. the time required to process the i 2 c buffer depends on other processes running inside the tpu firmware. thus the following i 2 c telegram addressing the tpu can be held after the slave address byte until the old telegram is completely processed. 3.14.1. subaddressing access to all memory locations and to the command interface is achieved by subaddressing. both the external dram and the internal cpu memory can be addressed completely. the tpu acknowledges 6 dif- ferent subaddresses following the slave address (see ta b le 3 ? 17 on page 85). the following symbols are used to describe the i 2 c example telegrams: < start condition > stop condition ab address bank byte ah address high byte al address low byte cc command byte dd data byte ss status byte .. 0 ? n continuation bytes table 3 ? 17: i 2 c bus subaddresses name binary value hex value mode function tpu 0010 001x 22, 23 w, r tpu slave address sub 1 0111 1000 78 w subaddressing cpu (static) sub 2 0111 1001 79 w subaddressing cpu (autoincrement) sub 3 0111 1010 7a w subaddressing dram (autoincrement) sub 4 0111 1011 7b w subaddressing command language data 0111 1100 7c r/w subaddressing data register status 0111 1101 7d r status register bit 7 = command wait bit 6 = command invalid bit 5 = command found no data bit 4 = not used bit 3 = not used bit 2 = not used bit 1 = 0 bit 0 = 0
vct 38xxa/b preliminary data sheet 86 micronas 3.14.1.1. cpu subaddressing there are 2 cpu subaddresses to access cpu mem- ory: either with static memory address or with autoin- crementing memory address. the main purpose of cpu subaddressing is to write text into the osd buffer and to access the i/o page (see section 3.13. on page 78). the static cpu subaddress can be used to write more than 1 byte into the same i/o page register. the cpu subaddress has to be followed by 2 address bytes defining the cpu memory address. the follow- ing data byte is written into this address. in the case of autoincrement the continuation bytes are written into incrementing memory addresses. the cpu telegram can be stopped after the 2 memory address bytes. the following i 2 c telegram subad- dressing the data register will continue data transfer to or from the cpu memory. the data transfer will always start at the cpu memory address (autoincrement is not saved). < 22 78 ah al dd .. > < 22 79 ah al dd .. > < 22 79 ah al > < 22 7c dd .. > data is directly written into cpu memory without using the i 2 c buffer of tpu and without waiting for a stop condition. 3.14.1.2. dram subaddressing dram access is necessary to generate level 2 dis- plays. the external dram can be addressed on byte level. the maximum dram size of 16 mbit requires a 21-bit memory address pointer. the format of the dram address pointer is shown in fig. 3 ? 22. fig. 3 ? 22: dram address pointer the dram subaddress has to be followed by 3 address bytes defining the dram address pointer. the following data byte is written into this address. dram subaddressing always uses autoincrement. separate read and write dram address pointers are saved for autoincrement. the dram telegram can be stopped after the 3 address pointer bytes. the following i 2 c telegram sub- addressing the data register will continue data transfer to or from the dram. when reading the dram, the first data byte the tpu returns is a dummy byte, which has to be ignored. < 22 7a ab ah al dd .. > < 22 7a ab ah al > < 22 7c dd .. > < 22 7a ab ah al > < 22 7c < 23 dd ..> data written to the dram subaddress is collected first in the i 2 c buffer of tpu and is copied to dram when the buffer is full (48 bytes) or after stop condition. dur- ing the time the buffer is copied to dram the tpu will hold the i 2 c clock line down. reading data from the dram subaddress is also buff- ered internally. reading the first byte will only empty the i 2 c buffer. every time the buffer is empty, the tpu will copy 48 bytes from dram into the i 2 c buffer. during this time the tpu will hold the i 2 c clock line down. 3.14.1.3. command subaddressing tpu supports a command language, allowing the host controller to start complex processing inside the tpu with simple commands (see section 3.12. on page 70). commands have to be sent to the command subaddress. the command subaddress has to be followed by the command code. the following data bytes are taken as command parameters. the execution time for commands depends on other processes running inside the tpu firmware, therefore the host controller has to read the status register to get information about the running command before read- ing command parameter or starting other commands. the status register returns information about the com- mand interface. the ? command wait ? bit is set during execution of a command and is reset when a com- mand is executed completely and read parameters are available. if a non-existing command is sent to the tpu, the ? command invalid ? bit is set. if a command could not be executed successfully, the ? command found no data ? bit is set. in this case the read parame- ters of this command are not valid. reading status from tpu is done by subaddressing the status register followed by repeated start condition and slave read address (see fig. 3 ? 23). < 22 7b cc dd .. > < 22 7d < 23 ss .. > < 22 7c < 23 dd .. > telegrams subaddressing the command interface are buffered and processed after receiving the stop condi- tion. therefore the command code and all necessary command parameters have to be included in a single telegram. 5-bit bank 8-bit high 8-bit low
preliminary data sheet vct 38xxa/b micronas 87 3.14.1.4. data subaddressing writing data to tpu memory is possible by subad- dressing the data register directly. the data is then written into memory addressed by the foregoing tele- gram. < 22 7c dd .. > reading data from tpu is done by subaddressing the data register followed by a repeated start condition and slave read address (see fig. 3 ? 23). the returned data depend on the subaddress selected in the pre- ceding tpu telegram. < 22 7c < 23 dd .. > fig. 3 ? 23: i 2 c bus protocol 3.14.1.5. hardware identification a separate i 2 c bus slave register is reserved to read out the hardware version of vct 38xxa/b. this regis- ter is active in standby mode. p s 1 0 sda scl w r ack nak s p = = = = = = 0 1 0 1 start stop = = interrupt data from tpu sack wacks sack wacks sack wack sack wack sack wack sack wack ack ack r r ack p ack p ack p ack p ack 0010001 0010001 0010001 0010001 0010001 0010001 0111 1000 0111 1001 0111 1011 0111 1010 0111 1100 0111 1101 n byte sub 2 n byte sub 3 n byte sub 4 n byte data n byte sub 1 0111 1100 0010001 0010001 ack nak nak p p n ? 1 byte data last byte data status status sack wackackp 0010001 i 2 c sub address number of bits mode function default name h ? 9f 16 r hardware version number bit[7:0] hardware id (a3=h ? 13, b1=h ? 21 a.s.o.) bit[15:8] product code vct 38xx (vct 3832=h ? 32) read only hwid tc prod
vct 38xxa/b preliminary data sheet 88 micronas 4. audio processing 4.1. introduction the audio processing allows input selection and vol- ume control for mono audio sources either from tuner or from scart input. fig. 4 ? 1: audio processing 4.2. input select both audio output channels can be switched to any of the three audio input channels. only the audio output channel aout1 can be volume controlled. 4.3. volume control the analog volume control covers a range from +18 db and ? 75 db. the lowest step is the mute posi- tion. step size is split into a 3-db and a 1.5-db range. ? 75 db... ? 54 db : 3 db step size ? 54 db...+18 db : 1.5 db step size 4.4. i 2 c-bus slave interface the input selection and analog volume is controlled via the audio control register acon. this i 2 c register is activated by the chip address of the video back-end processing (see table 2 ? 2 on page 31). aout1 ain3 ain1 ain2 aout2 table 4 ? 1: audio control register i 2 c sub address number of bits mode function default name h ? 34 16 w audio control bit [5:0] volume control 000000 mute 000001 ? 75db ... 000111 ? 57.0db 001000 ? 54.0db ... 101011 ? 1.5db 101100 0.0db 101101 +1.5db ... 110110 +15.0db 110111 +16.5db 111000 +18.0db bit [7:6] reserved bit [9:8] audio input select 1 00 mute 01 ain1 10 ain2 11 ain3 bit [11:10] audio input select 2 00 mute 01 ain1 10 ain2 11 ain3 bit[12] low power mode 0 disable low power mode 1 enable low power mode bit[15:13] reserved 0acon avol asel1 asel2 alpm
preliminary data sheet vct 38xxa/b micronas 89 5. tv controller 5.1. introduction the tv controller basically consists of the cpu, ram, rom, and a number of peripheral modules. for instance: ? a memory banking module is included to allow access to more than 64 kb memory. ? a bootloader software is included to allow in-sys- tem-downloading of external code to flash memory via the i 2 c interface. the tv controller runs the complete software neces- sary to control a tv set. the software includes control of the audio, video, osd, and text processors on chip, as well, as control of external devices like tuner or ste- reo decoder. communication between the tv controller and exter- nal devices is done either via i 2 c bus interface or via programmable port pins. the tv controller is clocked with f osc = f xtal /2. 5.2. cpu the cpu is fully compatible to wdc ? s w65c02 micro- processor. the processor has 8-bit registers/accumu- lator, an 8-bit data bus, and a 16-bit address bus. for further information about the cpu core, please refer to the wdc w65c02 data sheet. 5.2.1. cpu slow mode to reduce power consumption considerably, the user can reduce the internal cpu clock frequency to 1/256 of the normal f cpu value. in this cpu slow mode, pro- gram execution is reduced to 1/256 of the normal speed, but clocking of most other modules remains unaffected. the modules that are affected by cpu slow mode are 1. cpu and interrupt controller with all internal and external interrupts 2. ram, rom and dma 3. watchdog some modules must not be operated during cpu slow mode. refer to module sections for details. after reset the cpu is in fast mode (f cpu = f osc ). cpu slow mode is enabled by clearing flag cpufst in standby register sr1. the cpu clock frequency reduction to f osc /256 will take effect after a maximum delay of 256 f osc periods. returning cpu to fast mode is done by setting flag cpufst to high. the cpu clock frequency will imme- diately change to its normal f osc value. fig. 5 ? 1 shows the memory access signals during cpu fast and slow mode. fig. 5 ? 1: memory access signals f osc ph2 rw we oe fast mode slow mode ccuph2
vct 38xxa/b preliminary data sheet 90 micronas 5.3. ram and rom on-chip ram is composed of static ram cells. the ram will hold all information during reset, as long as the specified operating voltages are available. the 64psdip multi chip module (vct 38xxf) con- tains a 128-kbyte flash eeprom of the st m29w010b type. these devices exhibit electrical byte program and block erase functions. refer to the st m29w010b data sheet for details. 5.3.1. address map the following rom addresses are reserved and can- not be used to store program code. a 16-byte address space is reserved as ? manufacturer rom id ? . this area contains a unique rom id number which has to be agreed between micronas and the customer. especially the first 6 digits identify customer and version. as an example a micronas demo soft- ware is identified like ? mi1108 240700 tv ? . table 5 ? 2 shows the internal memory segmentation. internal program ram and rom can be disabled via the control register (chapter 5.4. on page 91). the internal text ram can be disabled via standby regis- ter 0 (see page 93). all memory locations not available internally will be addressed as external memory. it is possible to oper- ate with internal and external memory in parallel, but overlapping memory segments will always be addressed internally. during internal memory access, the pins db0-db7, wexq and oexq are tristate. for emulation and test purposes it is possible to change this behavior via the control register (see page 91). 5.3.2. bootloader a segment of the internal rom is reserved for boot- loader code. via this bootloader code it is possible to download additional code into the internal ram and execute this code. the downloaded code can be used to program the external flash eeprom. after reset the bootloader checks the i 2 c bus pins sda and scl for a special identification sequence. if no identification sequence is detected, the bootloader starts the application program code. the bootloader checks the address ffd6/ffd7 of the external memory if there is a predefined pattern (a55ah). if so, it starts the external application soft- ware else it starts the internal application software. table 5 ? 1: reserved (physical) addresses addresses usage 00ffc6 ? 00ffd5 manufacturer rom id 00ffd6 ? 00ffd7 reserved for bootloader 00ffd8 ? 00fff7 interrupt vectors 00fff8 reserved 00fff9 control word (during reset) 00fffa ? 00fffb nmi vector (expanded by interrupt controller) 00fffc ? 00fffd reset vector 0xfffe ? 0xffff irq/brk vector table 5 ? 2: internal memory locations addresses internal memory 000000 ? 000fff 4k program ram 001e00 ? 001fff i/o register 002000 ? 0023ff 1k bootloader rom 002400 ? 019fff 95k program rom 0a0000 ? 0a3fff 16k text ram at vct 383ya/b 0a0000 ? 0a0fff 4k text ram at vct 380yb
preliminary data sheet vct 38xxa/b micronas 91 5.4. control register the control register cr serves to configure the ways, by which certain system resources are accessed dur- ing operation. the main purpose is to obtain a variable system configuration during ic test. upon each high transition on the resq pin internal hardware reads data from address location 00fff9h and stores it to the cr. the state of the disintrom pin at this timepoint specifies which program storage source is accessed for this read: ? with disintrom pin low, the control byte is read from internal program memory (mask rom). with location 00fff9h set to ffh, this is the setting for stand-alone operation. ? with disintrom pin high, the control byte is read from external program memory. the system will thus start up according to the configuration defined in address location 00fff9h and automatically cop- ied into register cr. reslng reset pulse length r/w1: pulse length is 4095/f osc . r/w0: pulse length is 16/f osc . this bit specifies the length of the reset pulse which is output at pin resq following an internal reset. if pin test is 1 the first reset after power on is short. the following resets are as programmed by reslng. if pin test is 0 all resets are long. tsttog test pin toggle r/w1: pin test can toggle the multi function pins. r/w0: pin test can ? t toggle the multi function pins. this bit is used for test purposes only. if tsttog is true in ic active mode, pin test can toggle the multi function pins between bus mode and normal mode. enext disable external memory access r/w1: db0 ? db7, wexq and oexq output pins are active during external memory access (see fig. 5 ? 2 on page 92). r/w0: db0 ? db7, wexq and oexq output pins are inactive during external memory access. mfm multi function pin mode r/w1: enable normal mode. r/w0: enable test bus mode. tstrom test rom (mask rom parts only) r/w1: disable internal test rom. r/w0: enable internal test rom (@ irom=1). irom internal rom r/w1: enable internal cpu rom. r/w0: disable internal cpu rom. iram internal ram r/w1: enable internal cpu ram. r/w0: disable internal cpu ram. icpu internal cpu r/w1: enable internal cpu. r/w0: disable internal cpu. 1: 1f01 2: cr 3: control register bit76543210 r/w reslng tsttog enext mfm tstrom irom iram icpu reset value of 00fff9h
vct 38xxa/b preliminary data sheet 92 micronas fig. 5 ? 2: internal/external memory access ph2 rw adb db oe we db oe we extern extern intern intern internal signal controlword enext= 1 controlword enext= 0 internal signal
preliminary data sheet vct 38xxa/b micronas 93 5.5. standby registers the standby registers allow the user to switch on/off power or clock supply of single modules. with these flags it is possible to greatly influence power consump- tion and its related electromagnetic interference. for details about enabling and disabling procedures and the standby state refer to the specific module descriptions. the minimum ic current consumption is obtained with all standby registers set to 00h. pwm1 pulse width modulator 1 r/w1: module active. r/w0: module off. pwm0 pulse width modulator 0 r/w1: module active. r/w0: module off. tram text ram r/w1: module active r/w0: module off ccc capture compare counter r/w1: module active. r/w0: module off. tvpwm tuning voltage pulse width modulator r/w1: module active. r/w0: module off. cpufst cpu fast mode r/w1: fast mode: f cpu = f xtal / 2 r/w0: slow mode: f cpu = f xtal / 512 adc adc module r/w1: module active. r/w0: module off. tim1 timer 1 r/w1: module active. r/w0: module off. tim0 timer 0 r/w1: module active. r/w0: module off. pwm3 pulse width modulator 3 r/w1: module active. r/w0: module off. pwm2 pulse width modulator 2 r/w1: module active. r/w0: module off. i2c i 2 c-bus master interface r/w1: module active. r/w0: module off. mb memory banking r/w1: module active. r/w0: module off. 4: 1f08 5: sr0 6: standby register 0 bit76543210 r/w pwm1 pwm0 tram ccc tvpwm reset00000000 7: 1f09 8: sr1 9: standby register 1 bit76543210 r/w cpufst adc tim1 tim0 reset01000000 10: 1f0a 11: sr2 12: standby register 2 bit76543210 r/w pwm3 pwm2 i2c mb reset00000000
vct 38xxa/b preliminary data sheet 94 micronas 5.6. test registers test registers are for manufacturing test only. they must not be written by the user with values other than their reset values (00h). they are valid independent of the test input state. in all applications where a hardware reset may not occur over long times, it is good practice to force a software reset on these registers within appropriate intervals. 13: 1ffe 14: tst1 15: test register 1 bit76543210 w for testing purposes only reset00000000 16: 1fff 17: tst2 18: test register 2 bit76543210 w for testing purposes only reset00000000 19: 1ffd 20: tst3 21: test register 3 bit76543210 w for testing purposes only reset00000000 22: 1ffc 23: tst4 24: test register 4 bit76543210 w for testing purposes only reset00000000 25: 1ffb 26: tst5 27: test register 5 bit76543210 r for testing purposes only reset00000000
preliminary data sheet vct 38xxa/b micronas 95 5.7. reset logic 5.7.1. alarm function an alarm comparator on the pin resq allows the detection of a threshold higher than the reset thresh- old. an alarm interrupt can be triggered with the output of this comparator. the interrupt source output of this module is routed to the interrupt controller logic. but this does not neces- sarily select it as input to the interrupt controller. check section ? interrupt controller ? for the actually selectable sources and how to select them. the intended use of this function is made, when a sys- tem uses a 3.3 v regulator with an unregulated input. in this case, the unregulated input, scaled down by a resistive divider, is fed to the resq pin. with falling regulator input voltage this alarm interrupt is triggered first. then the reset threshold is reached and vct 38xxa/b is reset before the regulator drops out. the time interval between the occurrence of the alarm interrupt and the reset may be used to save process data to nonvolatile memory. in addition, power saving steps like turning off other devices may be taken to increase the time interval until reset. the alarm inter- rupt is a level triggered interrupt. the interrupt is active as long as the voltage on pin resq remains between the two thresholds of alarm and reset (see fig. 5 ? 3 on page 96). 5.7.2. software reset the tv controller software can generate a reset via the reset control register (see page 98). to prevent the tv controller from carrying out a reset in this case, the internal cpu reset can be disconnected from the resq pin. 5.7.2.1. from standby into normal mode to switch the whole tv application from standby oper- ation into normal mode the controller has to perform the following sequence: ? rc.resdis = 1, rc.dcoclp = 1 ? rc.resout =1 ? switch on power supply ? wait for stable power supply ? rc.selclk = 1, rc.i2cen = 1 ? rc.dcoclp = 0, rc.resout = 0 ? wait for rc.ali = 0 (ext. capacitor!) ? rc.resdis = 0 ? init dma interface ? init tpu, vdp and audio ? init external devices 5.7.2.2. from normal into standby mode to switch the whole tv application from normal mode into standby operation the controller has to perform the following sequence: ? rc.dcoclp = 1, rc.i2cen = 0 ? wait 1ms for stable 20.25mhz dco ? rc.selclk = 0 ? rc.resdis = 1 ? rc.resout = 1 ? disable ccm interrupt ? turn off power supply ? set tpu into standby mode ? sr0 = 2, sr1 = 8, sr2 = 0
vct 38xxa/b preliminary data sheet 96 micronas 5.7.3. internal reset sources the vct 38xxa/b contains three internal circuits that are able to generate a system reset: watchdog, supply supervision, and clock supervision. all internal resets are directed to the open drain output of pin resq. thus a ? wired or ? combination with exter- nal reset sources is possible. the resq pin is current limited and therefore large external capacitances may be connected. all internal reset sources initially set a reset request flag. this flag activates the pull-down transistor on the resq pin. an internal reset prolongation counter starts, as soon as no internal reset source is active any more. it counts 4096 f cpu periods (for alternative set- tings refer to register cr) and then resets the reset request flag, thus releasing the resq pin. 5.7.3.1. supply supervision an internal bandgap reference voltage is compared to vsup s . a vsup s level below the supply supervision threshold v refpor will permanently pull the pin resq low and thus hold the vct 38xxa/b in reset state (see fig. 5 ? 3 on page 96). this reset source is active after reset and can be enabled/disabled by flag csa in reg- ister csw0. 5.7.3.2. clock supervision the clock supervision monitors the cpu clock fre- quency f cpu . a frequency level below the clock super- vision threshold of approx. 200 khz will permanently pull the pin resq low and thus hold the ic in reset (see fig. 5 ? 3 on page 96). this reset source is active after reset and can be enabled/disabled by flag csa in register csw0. a frequency exceeding the specified clock frequency is not detected. fig. 5 ? 3: block diagram of reset logic voltage supervision & > 1 + - sq r clock supervision reset extension 16 or 4096 oscillator pulses watchdog + - vsup s v refpor bandgap v refa v refr v refpor v refa v refr resq > 1 & csw0.csa > 1 + - > 1 reset interrupt source rc.resout > 1 cpu reset rc.resdis vsup d > 1 tpu watchdog rc reset control reset internal reset to dma, tpu, vdp rc.vsi rc.tpui rc.ali
preliminary data sheet vct 38xxa/b micronas 97 5.7.3.3. watchdog the watchdog module serves to monitor undisturbed program execution. a failure of the program to retrig- ger the watchdog within a preselectable time will pull the resq pin low and thus reset the vct 38xxa/b (see fig. 5 ? 3 and fig. 5 ? 4). the watchdog reset source is only enabled after the first write access to register csw1 (see section 5.7.6. on page 98). once the watchdog is enabled, it cannot be dis- abled anymore, neither by software nor by pulling down the external resq pin. only after power up the watchdog is disabled. the watchdog contains a down-counter that gener- ates a reset when it wraps from zero to ffh. it is reloaded with the content of the watchdog timer regis- ter, when, on a write access to register csw1, watch- dog trigger registers 1 and 2 contain bit complemented values. resetting the vct 38xxa/b initializes the watchdog timer register to ffh, thus forcing the watchdog to create a maximum reset interval. the watchdog is controlled by register csw1. the first write access to it loads the timer register value set- ting the watchdog ? s unretriggered reset interval. the desired interval can be programmed by setting the csw1 value to: the resolution of the watchdog is 8192/f cpu . in cpu slow mode (see section 5.2.1. on page 89), the watchdog is clocked with the reduced cpu clock. the second and all following even numbered write accesses load watchdog trigger register 1, the third and all following odd numbered write accesses load watchdog trigger register 2. in all future, the cpu has to write alternatingly to regis- ter csw1 value and bit complement value, thus retrig- gering the up-counter. failure to retrigger will result in an overflow of the up-counter generating a watchdog reset. it is not allowed to change a chosen value. writing a wrong value to csw1 immediately sets the flag csw1.wdres and prohibits further retriggering of the watchdog counter. csw1.wdres is true after a watchdog reset. only a supply supervision reset or a write access to register csw1 clears it. fig. 5 ? 4: block diagram of watchdog value interval f cpu 8192 ----------------------------------- -1 ? = trigger reg1 timer register trigger reg2 8-bit-counter 2.write 3.write 1. write 8 1 8 8 zero reset out load reset in write csw1 power on sq r csw1.wdres csw1 & even & odd csw1 csw1 & sq r & = 1. write 1 clk = f cpu /8192 1. write c q s 1 & d 2.write & even 3.write & odd
vct 38xxa/b preliminary data sheet 98 micronas 5.7.4. external reset sources as long as the reset input comparator on the pin resq detects the low level, the vct 38xxa/b is in reset state. on this pin, external reset sources may be wire-ored with the internal reset sources, leading to a system-wide reset signal combining all system reset sources. 5.7.5. summary of module reset states after reset, the controller modules are set to the follow- ing reset states: 5.7.6. reset registers this register controls the reset logic and clock genera- tion. ali alarm interrupt r1: alarm was interrupt source r0: no pending alarm interrupt w1: reset alarm interrupt vsi vsup d voltage supervision interrupt r1: vsup d supervision was interrupt source r0: no pending vsup d supervision interrupt w1: reset vsup d supervision interrupt tpui tpu watchdog interrupt r1: tpu watchdog was interrupt source r0: no pending tpu watchdog interrupt w1: reset tpu interrupt flag if the source of one of these interrupts is still active, resetting the interrupt flag will not work and no further interrupt will be generated. i2cen i2c enable r/w1: enable i2c output from fe/be. r/w0: disable i2c output. dcoclp dco clamping r/w1: dco input clamped to 0. r/w0: dco input controlled by front-end. selclk select clock source r/w1: from pll. r/w0: from dco. resdis reset disable r/w1: disable internal cpu reset. r/w0: enable internal cpu reset. resout resq output w1: resq output active. w0: resq output inactive. this register controls the supply and clock supervi- sion modules. it can only be changed as long as the watchdog is disabled. csa clock and supply supervision active w1: both enabled. w0: both disabled. this register controls the watchdog module. only val- ues between 1 and 255 are allowed. wdres watchdog reset source r1: watchdog was reset source. w: any write access to csw1 resets this flag. first write the desired watchdog time value to this reg- ister. on further writes, to retrigger the watchdog, alternatingly write a value (not necessarily the former time value) and its bit complemented value. never change the latter value. table 5 ? 3: status after reset module status cpu cpu fast mode. interrupt controller interrupts are disabled. priority registers, request flip-flops and stack are cleared. ports normal mode. output is tristate. watchdog switched off. sw activation is possible. clock & supply supervision active. sw may toggle. 28: 1f07 29: rc 30: reset control register bit76543210 w ali vsi tpui i2cen dcoclp selclk resdis resout r ali vsi tpui i2cen dcoclp selclk resdis 0 reset00001000 31: 1f00 32: csw0 33: clock, supply & watchdog regis- ter 0 bit76543210 w xxxxxxxcsa resetxxxxxxx1 34: 1f60 35: csw1 36: clock, supply & watchdog regis- ter 1 bit76543210 r xxxxxxxwdres w watchdog time and trigger value reset11111111
preliminary data sheet vct 38xxa/b micronas 99 5.8. memory banking the 8-bit processor w65c02 only allows access to 64 kbyte of memory space. to allow access to the expanded memory range above 64 kbyte, a specific banking hardware is implemented. the physical address range above 32 kbytes (a15 = 1) is separated into several banks of which only one at a time is enabled and selected by the banking register (br), which is programmable as any other standard periph- eral register by writing the desired value into its spe- cific address. the content of the br is also readable, so the software may check the current bank at any time. the applied software is responsible to program the br with the correct bank number at the right time. since the upper 32 kbytes range is switched immedi- ately after programming the br, correct function is not guaranteed if it is changed by a program sequence running in a switched bank. br settings need to be done in the lower 32 kbytes (a15 = 0), which is the non-switchable master bank (bank 0). setting bn = 0 should be avoided because it will mirror the non-switchable master bank (bank 0) into the upper 32-kbyte area (a15 = 1). ram, i/o pages and reserved addresses may be manipulated unintention- ally. reset initializes bn = 1 to read control byte and reset vector from bank 1. also, interrupt vectors have to reside in bank 1, because the interrupt controller gen- erates the appropriate address of bank 1, but it does not change the contents of the br. interrupt functions have to reside in the non-switchable master bank (bank 0). otherwise, they need to be in each used bank, because after getting the vector the unchanged contents of the br determine the current bank which is valid if a15 is ? 1 ? . 5.8.1. banking register bn bank number r/w: number of 32 kbyte memory bank fig. 5 ? 5: block diagram of memory banking 37: 1f0f 38: br 39: banking register bit76543210 r/w bn reset00000001 a0 ... a14 b anking r egister a15 ... a19 65c02 *a0 ... a14 *a15 *d0 ... d7 interrupt controller, a0 ... a14 a15 ... a19 address decoder, memory, i/o *processor internal bus dma logic
vct 38xxa/b preliminary data sheet 100 micronas fig. 5 ? 6: memory banking shown with the maximal size of addressable memory bank 31 bank 21-30 bank 20 bank 17-19 bank 16 080000h 084000h 087fffh 0a8000h 0f8000h 0a0000h 088000h cpu ram/rom text ram tpu address space page ta b l e page memory osd bank scratch int. rom ttx bank dma ext. ram int. ram ext. rom bank 0 bank 1 bank 2 bank 3 bank 4 bank 5-14 000000h 004000h 003000h 002000h 001000h 07ffffh 000000h 000fffh 001e00h 008000h 00ffffh 002000h i/o-reg 078000h bank 15 page ta b le 000000h scratch 001000h page memory 001800h osd&ttx bank 004000h 020000h 128kbyte 256kbyte 512kbyte 040000h 16kbyte reserved 19k text ram 128k text ram page table 000000h scratch 001000h page memory 001800h 16k text ram 003000h osd&ttx bank
preliminary data sheet vct 38xxa/b micronas 101 5.9. dma interface the dma interface connects the tpu sram interface to the cpu memory bus (see fig. 5 ? 7). this is done to avoid extra pins for external tpu page memory. the dma interface must not be operated during cpu slow mode. the dma interface can be disabled via dmaim.dmaen. as long as the dma interface is disabled, the tpu cannot access the cpu address bus and therefore should not transfer data to/from the internal/external sram. to ensure this, the controller should reset the tpu before disabling the dma interface. after reset the tpu will not access the memory until receiving the i 2 c command ? dram_mode ? (see section 3.12. on page 70). in general, all tpu addresses are mapped into bank 16 to 31 of the cpu address space by forcing the msb of the address bus to ? 1 ? (see fig. 5 ? 8). additionally 4 memory segments can be mapped into any address area by programming a set of dma registers (see fig. 5 ? 9). special care should be taken when mapping tpu addresses into the ram area of bank 0. any over- lap between tpu memory (e.g. osd bank) and controller memory (e.g. non zero page variables) must be avoided. fig. 5 ? 7: block diagram of dma interface dma interface tpu sram interface cpu a[18:0] d[7:0] rwq ph2 rdy be rwq adb[19:0] db[7:0] rwq address mapping
vct 38xxa/b preliminary data sheet 102 micronas fig. 5 ? 8: dma address mapping if the mapping logic does not find any address match, the tpu address is directly put on the cpu address bus with a19 set to ? 1 ? . in case of multiple matches, the priority is map1 > map2 > map3 > map4. fig. 5 ? 9: dma mapping logic mux 1:5 decoder adb[19:8] a19 = ? 1 ? 3 12 match4 match3 match2 match1 12 12 12 12 12 map 1 map 2 map 3 map 4 a[18:8] tpu address bus & = 1 mask n cmp n map n match & & a[19:8] a[19:8] n: mapping logic 1 to 4 12 12 12 12
preliminary data sheet vct 38xxa/b micronas 103 5.9.1. dma registers ma19 to 8 mask address tpu address is masked with this value. ca19 to 8 compare address masked tpu address is compared with this value. mpa19 to 8 map address matching tpu address is replaced with this value. dmaen dma enable w1: enable dma interface w0: disable dma interface mapxe mapping logic x enable w1: enable mapping logic x w0: disable mapping logic x 40: 1e00 41: mask1l 42: mask 1 low byte 43: 1e01 44: mask2l 45: mask 2 low byte 46: 1e02 47: mask3l 48: mask 3 low byte 49: 1e03 50: mask4l 51: mask 4 low byte bit76543210 w ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 reset11111111 52: 1e04 53: mask1h 54: mask 1 high byte 55: 1e05 56: mask2h 57: mask 2 high byte 58: 1e06 59: mask3h 60: mask 3 high byte 61: 1e07 62: mask4h 63: mask 4 high byte bit76543210 w ma19 ma18 ma17 ma16 reset 1 1 1 1 64: 1e08 65: cmp1l 66: compare 1 low byte 67: 1e09 68: cmp2l 69: compare 2 low byte 70: 1e0a 71: cmp3l 72: compare 3 low byte 73: 1e0b 74: cmp4l 75: compare 4 low byte bit76543210 w ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 reset11111111 76: 1e0c 77: cmp1h 78: compare 1 high byte 79: 1e0d 80: cmp2h 81: compare 2 high byte 82: 1e0e 83: cmp3h 84: compare 3 high byte 85: 1e0f 86: cmp4h 87: compare 4 high byte bit76543210 w ca19 ca18 ca17 ca16 reset 1 1 1 1 88: 1e10 89: map1l 90: map 1 low byte 91: 1e11 92: map2l 93: map 2 low byte 94: 1e12 95: map3l 96: map 3 low byte 97: 1e13 98: map4l 99: map 4 low byte bit76543210 w mpa15 mpa14 mpa13 mpa12 mpa11 mpa10 mpa9 mpa8 reset11111111 100: 1e14 101: map1h 102: map 1 high byte 103: 1e15 104: map2h 105: map 2 high byte 106: 1e16 107: map3h 108: map 3 high byte 109: 1e17 110 : map4h 111 : map 4 high byte bit76543210 w mpa19 mpa18 mpa17 mpa16 reset 1 1 1 1 112: 1e18 113: dmaim 114: dma interface mode bit76543210 w dmaen map4e map3e map2e map1e reset0 0000
vct 38xxa/b preliminary data sheet 104 micronas 5.10. interrupt controller the interrupt controller has 16 input channels (see fig. 5 ? 10 on page 105). each input has its own inter- rupt vector pointing to an interrupt service routine (isr). one of 15 priority levels can be assigned to each input or the input can be disabled. the interrupt controller is connected to the nmi input of the cpu. but despite of the non-maskable interrupt input, it is possible to disable all interrupt sources in total in the interrupt controller. 5.10.1. features ? 16 interrupt inputs. ? 16 interrupt vectors. ? 15 individual priority levels. ? global/individual disable of interrupts. ? single interrupt service mode. 5.10.2. general interrupt requests are served in the order of their pro- grammed priority level. interrupt requests of the same priority level are served in descending order of inter- rupt input number. each of the 16 interrupt inputs clears a flag in the inter- rupt pending register (irret and irp), which can be read by the user. a pending interrupt enables the out- put of the corresponding priority register (irpri10 to irprife) which is connected to a parallel priority decoder together with the other priority registers. the decoder outputs the highest priority and its input num- ber to a latch. the latched priority is compared with the top entry of the priority stack. the top entry of the prior- ity stack contains the priority of the actual served inter- rupt. lower entries contain interrupts with lower priority whose interrupt service routines were started but inter- rupted by the higher priority interrupts above. if the latched priority is lower or equal than the top of stack priority, nothing happens. if the latched priority is higher than the top of stack priority, a nmi is sent to the cpu and the latched priority is pushed on the stack. the interrupt controller signals an interrupt by nmi input to the cpu. after the current instruction is fin- ished the cpu starts an interrupt sequence. first it puts the program counter high byte, then the program counter low byte and the program status register to the stack. then the cpu writes the vector address low byte (00fffah) to the bus. the interrupt control- ler recognizes this address and stops the cpu by the rdy signal. now the interrupt controller writes the vector address low and high byte of the correspond- ing interrupt number to the bus and releases the cpu by releasing rdy. the cpu now operates with the new vector of the interrupt service routine. when the interrupt controller writes the new vector to the address bus, the interrupt pending flag of this vec- tor is set, indicating that no interrupt is pending. the software must pull the top entry from the priority stack at the end of an interrupt service routine. this happens with the write access to the interrupt return register irret. then the next entry (with lower prior- ity) is visible at top of stack and is compared with the priority latch. the interrupt controller and related circuitry is clocked by the cpu clock and participates in cpu fast and slow mode. 5.10.3. initialization after reset, all internal registers are cleared but the interrupt controller is active. when an interrupt request arrives, it will be stored in the respective pend- ing register irp/irret. but it will not trigger an inter- rupt as long as its interrupt priority register irprixy is set to zero. proper sw configuration of the interrupt sources in peripheral modules has to be made prior to operation. before enabling individual inputs, make sure that no previously received signal on that input has cleared its pending flag which may trigger the interrupt controller. clear all pending interrupts with the flag irc.clear to avoid such an effect. 5.10.4. operation activation of an interrupt input is done by writing a pri- ority value ranging from 1h to fh to the respective irprixy register. upon an interrupt request, pending or fresh, the interrupt controller will immediately gen- erate an interrupt. during operation, changes in the priority register set- ting may be made to obtain varying interrupt servicing strategies. flags irc.daint, irc.dint and irc.a1int allow some variation in the interrupt con- troller response behavior. 5.10.5. inactivation there are two possibilities to disable an interrupt within the interrupt controller. changing the priority of an interrupt input to zero disables this interrupt locally. interrupts are globally disabled by writing a zero to flag irc.dint of register irc.
preliminary data sheet vct 38xxa/b micronas 105 pending register priority registers irpri10 irpri32 irprife fig. 5 ? 10: block diagram of interrupt logic r s q int-input 1 int-input 2 int-input 3 int-input 4 int-input 15 int-input 16 4 4 4 4 4 4 16 parallel priority decoder a>b a b interrupt vector tab l e 16 ctrl priority stack 15 x 4 rdy a0...a23 nmi clke priority latch enable 00fffa clke push irret write pull clear request input # prio 4 priority 4 4 a=b a b clke & clke dmae ph2 dmae r s q r s q r s q r s q r s q & ccunmidis ccunmi patch
vct 38xxa/b preliminary data sheet 106 micronas within the evaluation period (see section 5.10.10. on page 113) it ? s not possible to suppress an interrupt by changing priority. a zero in the flag irc.dint of register irc prevents the interrupt controller from pulling the signal nmi low. however, if this flag is set after the falling edge of nmi , the corresponding interrupt cannot be cancelled. 5.10.6. precautions the write access to the irret must be performed just before the rti command at the end of the interrupt service routine. after a write access to this location it is guaranteed that the next command (should be rti) will be processed completely before a new interrupt request is signaled to the cpu. if the rti command does not immediately follow the write to irret, an interrupt with the same priority may be detected before the corresponding rti is processed. a stack underflow may occur because this may happen several times. if an opcode fetch of a disable interrupt instruction (di) happens one clock cycle after the falling edge of nmi (see section 5.10.10. on page 113), it is possible, that an interrupt service routine (isr) is active, though the corresponding interrupt is disabled. that is why after disabling an interrupt, and before accessing critical data, at least one uncritical instruction is necessary. this guarantees that the isr is finished before critical data access and no further isr can interrupt it. because it is now possible that an isr can lengthen the time between di and enable interrupt (ei) indefi- nitely, it is necessary that an isr first saves registers and enables interrupt flags, and then enables inter- rupts. after interrupt execution, enable flags and regis- ters must be restored. this guarantees, that other interrupts are not locked out during interrupt execution. fig. 5 ? 11: interrupt service routine save registers execute interrupt restore registers write to irret rti
preliminary data sheet vct 38xxa/b micronas 107 5.10.7. interrupt registers reset reset w1: no action. w0: momentary reset of the interrupt control- ler, all internal registers are cleared. the reset of the interrupt controller happens with writ- ing zero to this flag. it is not necessary to write a one to finish the reset. the standard interrupt controller function is performed by setting all flags to one. a hardware reset of the interrupt controller is performed by setting the reset flag to low and the other flags to high. daint disable after interrupt r1: don ? t disable after interrupt. r0: disable interrupt controller after interrupt. w1: cancel this feature. w0: disable interrupt controller after interrupt. this is the enable flag for the flag a1int function. dint disable interrupt r1: interrupts are enabled. r0: all interrupts are disabled. w1: enable interrupts according to priority set- ting. w0: disable all interrupts. a1int allow one interrupt w1: no action. w0: serve one interrupt. this is a momentary signal. with daint = 0, only one interrupt (with the highest priority) will be served. the flags daint and a1int must be considered in common. they provide the possibility to serve inter- rupts one by one, only when the main program has enough time. clear clear all requests w1: no action. w0: momentarily clears all interrupt requests. ipf0 to 7 interrupt pending flag of input 0 to 7 r1: no interrupt is pending. r0: interrupt is pending. w: current request is finished. for interrupt pending flags 8 to 15 refer to description of register irp. 11 5: 1f20 11 6: irc 11 7: interrupt control register bit76543210 r xxxxdaintdintxx w x x x reset daint dint a1int clear reset x 1 1 x x table 5 ? 4: single interrupt service daint a1int resulting function 0 1 disable after current interrupt. 0 0 serve one interrupt request. 1 x normal interrupt mode. 11 8: 1f21 119: irret 120: interrupt return register bit76543210 r ipf7 ipf6 ipf5 ipf4 ipf3 ipf2 ipf1 ipf0 w a write access signals the interrupt controller that the current request has been served. reset00000000
vct 38xxa/b preliminary data sheet 108 micronas a write access to this memory location signals to the interrupt controller that the current request has been served. prion priority of interrupt input n r: priority of the corresponding interrupt input. w: priority of the corresponding interrupt input. priority zero prevents the interrupt controller from being triggered but the pending register is not affected. all incoming requests are stored in the pending regis- ters. with two inputs having the same prio setting, the higher numbered input has priority. ipf8 to 15 interrupt pending flag of input 8 to 15 r1: no interrupt is pending. r0: interrupt is pending. for interrupt pending flags 0 to 7 refer to description of register irret. 121: 1f22 122: irpri10 123: interrupt priority register, input 0 and 1 bit76543210 r/w prio1 prio0 reset00000000 124: 1f23 125: irpri32 126: interrupt priority register, input 2 and 3 bit76543210 r/w prio3 prio2 reset00000000 127: 1f24 128: irpri54 129: interrupt priority register, input 4 and 5 bit76543210 r/w prio5 prio4 reset00000000 130: 1f25 131: irpri76 132: interrupt priority register, input 6 and 7 bit76543210 r/w prio7 prio6 reset00000000 133: 1f26 134: irpri98 135: interrupt priority register, input 8 and 9 bit76543210 r/w prio9 prio8 reset00000000 136: 1f27 137: irpriba 138: interrupt priority register, input 10 and 11 bit76543210 r/w prio11 prio10 reset00000000 139: 1f28 140: irpridc 141: interrupt priority register, input 12 and 13 bit76543210 r/w prio13 prio12 reset00000000 142: 1f29 143: irprife 144: interrupt priority register, input 14 and 15 bit76543210 r/w prio15 prio14 reset00000000 table 5 ? 5: prion usage prion resulting function 0h interrupt input is disabled 1h interrupt input is enabled with lowest priority :: fh interrupt input is enabled with highest priority 145: 1f2a 146: irp 147: interrupt pending register bit76543210 r ipf15 ipf14 ipf13 ipf12 ipf11 ipf10 ipf9 ipf8 reset00000000
preliminary data sheet vct 38xxa/b micronas 109 5.10.8. interrupt assignment while most interrupt assignments are hard-wired, some can be configured by software (see fig. 5 ? 12 on page 110). the vsync interrupt is generated in the video pro- cessing block of the vdp. on vct 38xxa it is gener- ated in the 1st field only. on vct 38xxb it is generated in both fields and can be used to start an interrupt ser- vice routine which handles the closed caption module (see section 5.18. on page 133). 5.10.8.1. interrupt multiplexer interrupt inputs 0 ? 11 are directly connected to the respective module ? s interrupt output. four interrupt inputs 12 to 15 allow source selection via multiplexers. the source can be any of the 15 special input ports (see section 5.19.1. on page 137). the multiplexers are configured by registers irpmux0 and irpmux1. table 5 ? 6: interrupt assignment interrupt input interrupt vector address interrupt source 0 00fff6 ? f7 i2c 1 00fff4 ? f5 t0 2 00fff2 ? f3 t1 3 00fff0 ? f1 cccofl 4 00ffee ? ef cc0or 5 00ffec ? ed cc0comp 6 00ffea ? eb cc1or 7 00ffe8 ? e9 cc1comp 8 00ffe6 ? e7 tvpwm 9 00ffe4 ? e5 vsync 10 00ffe2 ? e3 reset 11 00ffe0 ? e1 cmpo 12 00ffde ? df pint0 13 00ffdc ? dd pint1 14 00ffda ? db pint2 15 00ffd8 ? d9 pint3
vct 38xxa/b preliminary data sheet 110 micronas fig. 5 ? 12: interrupt assignment and multiplexer mux 0 mux 1 mux 2 mux 3 interrupt controller special input ports 15 interrupt sources of peripheral modules trigger mode irpm0 0 1 1/4 irpp.p0int4 0 1 irpp.p1int32 1/32 12 pint0 pint1 pint2 pint3
preliminary data sheet vct 38xxa/b micronas 111 5.10.9. port interrupt module port interrupts are the interface of the interrupt con- troller to the external world. four port pins are con- nected to the module via their special input lines. port interrupt 0 and 1 can scale down the interrupt load by prescalers. port interrupt 2 and 3 are directly con- nected to the special input multiplexer. the user can define the trigger mode for each port interrupt by the interrupt port mode register. the port interrupt prescaler can be switched by the interrupt port prescaler register. the pulse duty factor of the prescaler output is 50 %. the trigger mode defines on which edge of the inter- rupt source signal the interrupt controller is triggered. the triggering of the interrupt controller is shown in fig. 5 ? 13 and fig. 5 ? 14 for port prescaler active (p1int32 or p0int4 = 1). pitn port interrupt trigger n this field defines the trigger behavior of the associated port interrupt. p1int32 port 1 interrupt prescaler w1: indirect mode, 1:32 prescaler w0: direct mode, bypass prescaler p0int4 port 0 interrupt prescaler w1: indirect mode, 1:4 prescaler w0: direct mode, bypass prescaler pisipn port interrupt special input port n this field defines the special input port connected to the associated port interrupt (see table on page 137). 148: 1f2b 149: irpm0 150: interrupt port mode bit76543210 w pit3 pit2 pit1 pit0 reset00000000 table 5 ? 7: pitn usage pitn trigger mode 0h interrupt source is disabled 1h rising edge 2h falling edge 3h rising and falling edges 151: 1f2c 152: irpp 153: interrupt port prescaler bit76543210 w xxxxxxp1int32p0int4 reset 0 0 154: 1e71 155: irpmux0 156: interrupt port multiplex 0 bit76543210 w pisip1 pisip0 reset00000000 157: 1e72 158: irpmux1 159: interrupt port multiplex 1 bit76543210 w pisip3 pisip2 reset00000000
vct 38xxa/b preliminary data sheet 112 micronas fig. 5 ? 13: interrupt timing (1/4 prescaler on) fig. 5 ? 14: interrupt timing (1/32 prescaler on) 12341234 1234 port px.y falling edge falling and rising independent interrupt (low active) interrupt (low active) 1/4 prescaler output of trigger mode edge trigger mode rising edge interrupt (low active) 32 1 2 15 16 31 32 port px.y falling edge trigger falling and rising independent interrupt (low active) interrupt (low active) 1/32 of trigger mode edge trigger mode prescaler output 17 18 rising edge trigger interrupt (low active)
preliminary data sheet vct 38xxa/b micronas 113 5.10.10. interrupt timing the interrupt response time is calculated from the interrupt event up to the first interrupt vector on the address bus (see fig. 5 ? 15 on page 113). after an interrupt event, the interrupt controller starts evaluation with the first falling edge of ph2. evaluation needs one clock cycle until the interrupt controller pulls the signal nmi low. after the falling edge of nmi the cpu finishes the actual command. if the falling edge of nmi happens one clock cycle before an opcode fetch, the following command will be finished too. then pc and status will be saved on stack before the low byte of the interrupt vector is written to the address bus. fig. 5 ? 15: interrupt timing diagram interrupt request nmi rdy clear request ph2 dmae interrupts finish actual command and save status. (save status = 5 clocks). enabled a0...23 interrupt 00fffa vector 2nd byte vector 1st byte dma opcode isr
vct 38xxa/b preliminary data sheet 114 micronas 5.11. memory patch module the memory patch module allows the user to modify up to ten hard-wired rom locations by external means. this function is useful if faulty parts of software or data are detected after the rom code has been cast into mask rom. software loads addresses and the corrected code e.g. from external non-volatile memory into respective registers of the module. the module then will replace faulty code upon address match. single rom locations are directly replaced. longer faulty sequences may be repaired by introducing a jump to a new subroutine in ram (e.g. opcode jsr requires 3 consecutive bytes to be patched). the ram subroutine then may consist of any number of instruc- tions, ending with a return to the next correct instruc- tion in rom. in such a way it is possible to include also complex software modules. 5.11.1. features ? patching of read data from up to 10 different rom locations (24 bit physical address) ? automatic insertion of 1 cpu wait state for each patched access 5.11.2. general the logic contains ten patch cells (see fig. 5 ? 16 on page 114), each consisting of a 24-bit compare regis- ter (patch address register, parn), a 24-bit address comparator, a patch enable register (pern) bit and an 8-bit patch data register (pdr). the current address information for a rom access is fed to a bank of ten patch cells. in case of a match in one patch cell, and provided that the corresponding patch enable register bit is set, a wait cycle for cpu is included by pulling down the rdy input of cpu for one cycle (see fig. on page 115). in the meantime the module ? s logic disables the rom data bus drivers and instead places the data information from the corre- sponding patch data register on the data bus. 5.11.3. initialization after reset, as bit per0.pmen is reset to 0, all patch cell registers are in write mode and patch operation is disabled. to initialize a patch cell, first set the corresponding psel bit in register per0 or per1 as a pointer. then enter the 24bit address to registers par2 (high byte), par1 (middle byte) and par0 (low byte) and the desired patch code to register pdr. if desired, repeat the above sequence for other patch cells. only set one psel pointer bit in registers per0 and per1 at a time. fig. 5 ? 16: block diagram of patch module pa[23:16] pa[7:0] adb[23:0] db[7:0] 1 pa[15:8] patch address register patch enable register output enable patch data patch cell 0 patch cells 1...9 register enable write /compare sequencer psel9...0 pmen dbp[7:0] rdy romen rwq romacc ph2 patoe &
preliminary data sheet vct 38xxa/b micronas 115 5.11.4. patch operation to activate a number of properly initialized patch cells for rom code patching, set all the corresponding psel bits in registers per1, then per0, setting bit per0.pmen to 1. the memory patch module will immediately start com- paring the current address to the setting of the enabled patch cells. in case of a match, the rom data will be replaced by the corresponding patch cell data register setting. to reconfigure the memory patch module, first set per0.pmen to 0. the module will immediately termi- nate patch operation. . fig. 5 ? 17: patch timing 5.11.5. patch registers pa23 to 0 patch address upon occurrence of this address the patch cell replaces rom data with data from pdr. pd7 to 0 patch data data to replace false rom data at certain address. psel0 to 9 select patch cell w1: select cell for write or enable for patch w0: disable patch cell before writing compare address or replace data of a patch cell, only one cell must be selected. in compare mode one or more patch cells can be selected. pmen patch mode enable w1: enable patch mode of all cells w0: enable write mode of all cells adb[23:0] rdy patoe db[7:0] romen ph2 a2 a2 a3 a1 a3 d2 d1 pd1 d3 pd2 160: 1e64 161: par0 162: patch address register 0 bit76543210 w pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset11111111 163: 1e65 164: par1 165: patch address register 1 bit76543210 w pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 reset11111111 166: 1e66 167: par2 168: patch address register 2 bit76543210 w pa23 pa22 pa21 pa20 pa19 pa18 pa17 pa16 reset 11111111 169: 1e67 170: pdr 171: patch data register bit76543210 w pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 reset 00000000 172: 1e68 173: per0 174: patch enable register 0 bit76543210 w psel6 psel5 psel4 psel3 psel2 psel1 psel0 pmen reset00000000 175: 1e69 176: per1 177: patch enable register 1 bit76543210 w x x x x x psel9 psel8 psel7 resetxxxxx000
vct 38xxa/b preliminary data sheet 116 micronas 5.12. i 2 c-bus master interface the i 2 c bus interface is a pure master system, multi- master busses are not realizable. the clock and data terminal pins have open-drain outputs. the i 2 c bus master interface can operate on two ter- minals. terminal 1 is connected to the pins sda/scl, terminal 2 can be connected either to the pins p36/p37 or to the pins p22/p23. please refer to chap- ter 5.19. on page 137 how to set up the corresponding port pins. the i 2 c bus master interface is not affected by cpu slow mode. the bit rate is programmable using a clock prescaler. a complete telegram is assembled by the software out of individual sections. each section contains an 8-bit data. this data is written into one of the six possible write registers. depending on the chosen address, a certain part of an i 2 c bus cycle is generated. by means of corresponding calling sequences it is there- fore possible to join even very long telegrams (e.g. long data files for auto increment addressing of i 2 c slaves). the software interface contains a 5 word deep write- fifo for the control data registers, as well, as a 3 word deep read fifo for the received data. thus most of the i 2 c telegrams can be transmitted to the hardware without the software having to wait for empty space in the fifo. an interrupt is generated on two conditions: ? the write-fifo was filled and reaches the ? half full ? state. ? the write-fifo is empty and stop condition is com- pleted. all address and data fields appearing on the bus are constantly monitored and written into the read-fifo. the software can then check these data in comparison with the scheduled data. if a read instruction is han- dled, the interface must set the data word ffh, so that the responding slave can insert its data. in this case the read-fifo contains the read-in data. if telegrams longer than 3 bytes (1 address, 2 data bytes) are received, the software must check the filling condition of the write-fifo and, if necessary, fill it up (or read out the read-fifo). a variety of status flags is available for this purpose: ? the ? half full ? flag i2crs.wfh is set if the write- fifo is filled with three bytes. ? the ? empty ? flag i2crs.rfe is set if there is no more data available in the read-fifo. ? the ? busy ? flag i2crs.busy is activated by writing any byte to any one of the write registers. it stays active until the i 2 c bus activities are stopped after the stop condition generation. moreover, the ack-bit is recorded separately on the bus lines for the address and the data fields. however, the interface itself can set the address ack=0. in any case the two ack flags show the actual bus condition. these flags remain until the next i 2 c start condition is generated. for example, the software has to work off the following sequence (ack = 1) to read a 16-bit word from an i 2 c device address 10h (on condition that the bus is not active): ? write 021h to i2cws0 ? write 0ffh to i2cwd0 ? write 0ffh to i2cwp0 ? read rfe bit from i2crs ? read dev. address from i2crd ? read rfe bit from i2crs ? read 1st data byte from i2crd ? read rfe bit from i2crs ? read 2nddata byte from i2crd the value 21h in the first step results from the device address in the 7 msbs and the r/w-bit (read=1) in the lsb. if the telegrams are longer, the software has to ensure that neither the write-fifo nor the read-fifo can overflow. ? to write data to this device: ? write 20h to i2cws0 ? write 1st data byte to i2cwd0 ? write 2nd data byte to i2cwp0 the bus activity starts immediately after the first write to the write-fifo. the transmission can be synchro- nized by an artificial extension of the low phase of the clock line. transmission is not continued until the state of the clock line is high once again. thus, an i 2 c slave device can adjust the transmission rate to its own abili- ties.
preliminary data sheet vct 38xxa/b micronas 117 fig. 5 ? 18: block diagram of i 2 c bus master interface address decoder wr_data (subaddress = control info) sr in out write fifo 5 x 11 wr d 0 to d 7 control read fifo 3 x 8 d 0 to d 7 read logic half full sr q sr q busy write logic empty start condition resets ack flags 2 2 terminal 1 sda/scl terminal 2 p22/p23 p36/p37 d 0 to d 7 rd_status dat_ack adr_ack i2c interrupt rd_data empty status register clk = f osc clock prescaler sr2.i2c 0 1
vct 38xxa/b preliminary data sheet 118 micronas fig. 5 ? 19: start condition i 2 c bus fig. 5 ? 20: single bit on i 2 c bus fig. 5 ? 21: stop condition i 2 c bus 5.12.1. i 2 c bus master interface registers writing this register moves i2c start condition, i2c address and ack=1 into the write fifo. writing this register moves i2c start condition, i2c address and ack=0 into the write fifo. writing this register moves i2c data and ack=1 into the write fifo. writing this register moves i2c data and ack=0 into the write fifo. writing this register moves i2c data, ack=1 and i2c stop condition into the write fifo. writing this register moves i2c data, ack=0 and i2c stop condition into the write fifo. 1t 1t 1/2t sda scl 1/4t repeated 8 times sda scl 1/2t 1/4t 1/4t 1t sda scl 3/4t 1/4t 178: 1fd0 179: i2cws0 180: i2c write start register 0 bit76543210 w i2c address reset00000000 181: 1fd1 182: i2cws1 183: i2c write start register 1 bit76543210 w i2c address reset00000000 184: 1fd2 185: i2cwd0 186: i2c write data register 0 bit76543210 w i2c data reset00000000 187: 1fd3 188: i2cwd1 189: i2c write data register 1 bit76543210 w i2c data reset00000000 190: 1fd4 191: i2cwp0 192: i2c write stop register 0 bit76543210 w i2c data reset00000000 193: 1fd5 194: i2cwp1 195: i2c write stop register 1 bit76543210 w i2c data reset00000000
preliminary data sheet vct 38xxa/b micronas 119 reading this register returns the content of the read fifo. oack ? or ? ed acknowledge r: aack || dack aack address acknowledge r: acknowledge state of address field dack data acknowledge r: acknowledge state of data field busy busy r1: i 2 c master interface is busy r0: i 2 c master interface is not busy wfh write-fifo half full r1: write-fifo is filled with 3 bytes r0: write-fifo is not half full rfe read-fifo empty r1: read-fifo is empty r0: read-fifo is not empty term terminal select w1: terminal 1 w0: terminal 2 speed speed select w: i 2 c bit rate = f osc / (4 * speed) sips special input port select w1: use port pair p36, p37 for terminal 2 w0: use port pair p22, p23 for terminal 2 196: 1fd6 197: i2crd 198: i2c read data register bit76543210 r i2c data reset00000000 199: 1fd7 200: i2crs 201: i2c read status register bit76543210 r x oack aack dack busy wfh rfe x reset00000000 202: 1fdb 203: i2cm 204: i2c mode register bit76543210 w term speed reset10000010 table 5 ? 8: i 2 c bit rates speed bit rate 0 19.776 kbit/s 1 2.531 mbit/s 2 1.266 mbit/s 3 844 kbit/s 4 633 kbit/s ... ... 127 19.931 kbit/s 205: 1e73 206: i2cps 207: i2c port select register bit76543210 w sips reset00000000
vct 38xxa/b preliminary data sheet 120 micronas 5.13. timer t0 and t1 timer t0 and t1 are 16-bit auto reload down counters. they serve to deliver a timing reference signal, to out- put a frequency signal or to produce time stamps. 5.13.1. features ? 16-bit auto reload counter ? time value readable ? interrupt source output ? frequency output 5.13.2. operation the timer ? s 16-bit down-counter is clocked by the input clock and counts down to zero. reaching zero, it gen- erates an output pulse, reloads with the content of the timx reload register and restarts its travel. t0 and t1 are not affected by cpu slow mode. the clock input frequency can be selected from three possible values by programming the timer mode regis- ter timxm.csf. after reset, both timers are in standby mode (inactive). prior to entering active mode, proper sw initialization of the ports assigned to function as tx-out outputs has to be made. the ports have to be configured spe- cial out (see section 5.19. on page 137). to initialize a timer, reload register timx has to set to the desired time value, still in standby mode. for enter- ing active mode, set the corresponding enable bit in the standby register. the timer will immediately start counting down from the time value present in register timx. during active mode, a new time value is loaded by writing to the 16-bit register timx, high byte first. upon writing the low byte, the reload register is set to the new 16-bit value, the counter is reset, and immediately starts down-counting with the new value. on reaching zero, the counter generates a reload sig- nal, which can be used to trigger an interrupt. the same signal is connected to a divide by two scaler to generate the output signal tx-out with a pulse duty factor of 50 %. the interrupt source output of this module is routed to the interrupt controller logic (see section 5.10. on page 104). the state of the down-counter is readable by reading the 16-bit register timx, low byte first. upon reading the low byte, the high byte is saved to a temporary latch, which is then accessed during the subsequent high byte read. thus, for time stamp applications, read consistency between low and high byte is guaranteed. returning a timer to standby mode by resetting the corresponding enable bit will halt its counter and will set its output to low. the register timx remains unchanged. fig. 5 ? 22: block diagram of timer t0 and t1 1/2 16 zero 16 bit auto-reload down counter reload-reg. tim x w r tim x tx interrupt source clk tx-out 3:1 mux f osc /2 1 f osc /2 9 f osc /2 17 2 timxm.csf sr1.timx 0 1
preliminary data sheet vct 38xxa/b micronas 121 5.13.3. timer registers timx have to be read low byte first and written high byte first. csf clock selection field r/w: source of timer clock (see table 5 ? 9) 208: 1f4e 209: tim0l 210: timer 0 low byte 211: 1f4c 212: tim1l 213: timer 1 low byte bit76543210 r read low byte of down-counter and latch high byte. w write low byte of reload value and reload down-counter. reset11111111 214: 1f4f 215: tim0h 216: timer 0 high byte 217: 1f4d 218: tim1h 219: timer 1 high byte bit76543210 r read latched high byte of down-counter. w write high byte of reload value. reset11111111 220: 1f11 221: tim0m 222: timer 0 mode 223: 1f13 224: tim1m 225: timer 1 mode bit76543210 r/w csf reset00000000 table 5 ? 9: csf usage csf clock divider timer clock timer increment timer period 00 f osc /2 1 5.0625 mhz 197.53 ns 12.945 ms 01 f osc /2 9 19.775 khz 50.568 s 3.3140 s 1x f osc /2 17 77.248 hz 12.945 ms 848.39 s
vct 38xxa/b preliminary data sheet 122 micronas 5.14. capture compare module (capcom) the capture compare module (capcom) is a com- plex relative timer. it comprises a free running 16-bit capture compare counter (ccc) and 2 capture com- pare subunits (su). the ccc provides an interrupt on overflow and the timer value can be read by software. a su is able to capture the relative time of an external event input and to generate an output signal when the ccc passes a predefined timer value. three types of interrupts enable interaction with sw. special function- ality provides an interface to the asynchronous exter- nal world. 5.14.1. features ? 16-bit free running counter with read out. ? 16-bit capture register. ? 16-bit compare register. ? input trigger on rising, falling or both edges. ? output action: toggle, low or high level. ? three different interrupt sources: overflow, input, compare ? designed for interfacing to asynchronous external events fig. 5 ? 23: block diagram of capcom module a b = & > 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 toggle low 76543210 76543210 2 msk msk msk fol cap cmp ofl lac rcr x x x 16-bit compare-register 16-bit capture-register r w 16 16 32 0 1 2 ofl cc0m cc0i cc0 > 1 load cc0comp cc0or iam oam & & reset output action logic input action logic interrupt source interrupt source 16 subunit 0 ccc clk cc0-in cc0-out 16 timer value subunit 1 cc1-in cc1-out sr0.ccc ofl timer value cccofl interrupt source cc1or interrupt source cc1comp interrupt source 2 cccs.csf 4:1 mux f osc /2 0 f osc /2 4 f osc /2 8 f osc /2 12 0 1
preliminary data sheet vct 38xxa/b micronas 123 5.14.2. initialization after system reset the ccc and all sus are in standby mode (inactive). in standby mode, the ccc is reset to value 0000h. capture and compare registers ccx are reset. no information processing will take place, e.g. update of interrupt flags. however, the values of registers ccxi and ccxm are only reset by system reset, not by standby mode. thus, it is possible to program all mode bits in standby mode and a predetermined start-up out of standby mode is guaranteed. prior to entering active mode, proper sw configuration of the ports assigned to function as input capture inputs and output action outputs has to be made. the output action ports have to be configured as special out and the input capture ports as special in (see section 5.19. on page 137). please note, that the compare register ccx is reset in standby mode. it can only be programmed in active mode. 5.14.3. operation of ccc for entering active mode of the entire capcom mod- ule set, the enable bit in the standby register. the ccc will immediately start up-counting with the selected clock frequency and will deliver this 16-bit value to the sus. the state of the counter is readable by reading the 16- bit register ccc, low byte first. upon reading the low byte, the high byte is saved to a temporary latch, which is then accessed during the subsequent high byte read. thus, for time stamp applications, read con- sistency between low and high byte is guaranteed. the ccc is free running and will overflow from time to time. this will cause generation of an overflow inter- rupt event. the interrupt (cccofl) is directly fed to the interrupt controller and also to all sus where fur- ther processing takes place. 5.14.3.1. operation of subunit f or a proper setup the sw has to program the follow- ing su control bits in registers ccxi and ccxm: inter- rupt mask (msk), force output logic (fol, 0 recom- mended), output action mode (oam), input action mode (iam), reset capture register (rcr, 0 recom- mended), and lock after capture (lac). refer to sec- tion 5.14.5. for details. each su is able to capture the ccc value at a point of time given by an external input event processed by an input action logic. a su can also change an output line level via an out- put action logic at a point of time given by the ccc value. thus, a su contains a 16-bit capture register ccx to store the input event ccc value, a 16-bit compare reg- ister ccx to program the output action ccc value, an 8-bit interrupt register ccxi and an 8-bit mode register ccxm. two types of interrupts per su enable interac- tion with sw. for limitations on operating the capcom module in cpu slow mode, see section 5.14.3.4. on page 124. 5.14.3.2. compare and output action to activate a sus compare logic the respective 16-bit compare register ccx has to be programmed, low byte first. the compare action will be locked until the high byte write is completed. as soon as ccx setting and ccc value match, the following actions are trig- gered: ? the flag cmp in the ccxi register is set. ? the ccxcomp interrupt source is triggered. ? the ccxor interrupt source is triggered when acti- vated. ? the output action logic is triggered. four different reactions are selectable for the output action signal: according to field ccxm.oam (table ) the equal state will lead to a high or low level, or toggling or inactivity on this output. another means to control the output action is bit ccxm.fol. e.g. rise-mode and force will set the output pin to high level, fall-mode and force to low level. this forcing is static, i.e. it will be permanently active and may override compare events. thus, it is recommended to set and reset shortly after that, i.e. to pulse the bit with sw. toggle mode of the output action logic and forcing leads to a burst with clock- frequency and is not recommended.
vct 38xxa/b preliminary data sheet 124 micronas 5.14.3.3. capture and input action the input action logic operates independently of the output action logic and is triggered by an external input in a way defined by field ccxm.iam. following table 5 ? 12 it can completely ignore events, trigger on rising or falling edge or on both edges. when trig- gered, the following actions take place: ? flag ccxi.cap is set. ? the ccxor interrupt source is triggered when acti- vated. ? the 16-bit capture register ccx stores the current ccc value, i.e. the ? time ? of the external event. read ccx low byte first. further compare action will be locked until the subsequent high byte read is completed. thus a coherent result is ensured, no matter how much time has elapsed between the two reads. some applications suffer from fast input bursts and a lot of capture events and interrupts in consequence. if the sw cannot handle such a rate of interrupts, this could evoke stack overflow and system crash. to pre- vent such fatal situations the lock after capture (lac) mode is implemented. if bit ccxi.lac is set, only one capture event will pass. after this event has triggered a capture, the input action logic will lock until it is unlocked again by writing an arbitrary value to register ccxm. make sure that this write only restores the desired setting of this register. programming the input action logic while an input tran- sition occurs may result in an unexpected triggering. this may overwrite the capture register, lock the input action logic if in lac mode and generate an interrupt. make sure that sw is prepared to handle such a situa- tion. for testing purposes, a permanent reset (ffffh) may be forced on capture register ccx by setting bit ccxi.rcr. make sure that the reset is only temporary. 5.14.3.4. interrupts each su supplies two internal interrupt events: 1. input capture event and 2. comparator equal state. as previously explained, interrupt events will set the corresponding flags in register ccxi. in addition to the above mentioned two, the ccc overflow interrupt event sets flag ccxi.ofl in each su. thus, three interrupt events are available in each su. the corre- sponding flags are masked with their mask bits in reg- ister ccxm and passed to a logical or. the result (ccxor) is fed to the interrupt controller as a first interrupt source. in addition, the comparator equal (ccxcomp) interrupt is directly passed to the interrupt controller as second interrupt source. thus a su offers four types of interrupts: ccc overflow (maskable ored), input capture event (maskable ored) and comparator equal state (maskable ored and non- maskable direct). all interrupt sources act independently, parallel inter- rupts are possible. the interrupt flags enable sw to determine the interrupt source and to take the appro- priate action. before returning from the interrupt rou- tine the corresponding interrupt flag should thus be cleared by writing a 1 to the corresponding bit location in register ccxi. the interrupts generated by internal logic (ccc over- flow and comparator equal) will trigger in a predeter- mined and known way. but as explained in 5.14.3.3. erroneous input signals may cause some difficulties concerning the input capture input, as well, as inter- rupt handling. to overcome possible problems the input capture interrupt flag ccxi.cap is double buff- ered. if a second or even more input capture interrupt events occur before the interrupt flag is cleared (i.e. sw was not able to keep track), the flag goes to a third state. two consecutive writes to this bit in register ccxi are then necessary to clear the flag. this enables sw to detect such a multiple interrupt situation and eventually to discard the capture register value which always relates to the latest input capture event and interrupt. the internal capcom module control logic always runs on the oscillator frequency, regardless of cpu slow mode. avoid write accesses to the ccxi register in cpu slow mode, since the logic would interpret one cpu access as many consecutive accesses. this may yield unexpected results concerning the functionality of the interrupt flags. the following procedure should be followed to handle the capture interrupt flag cap: 1. sw responds to a capcom interrupt, switching to cpu fast mode if necessary and determining that the source is a capture interrupt (cap flag =1). 2. the interrupt service routine is processed. 3. just before returning to main program, the service routine acknowledges the interrupt by writing a 1 to flag cap. 4. the service routine reads cap again. if it is reset, the routine can return to main program as usual. if it is still set an external capture event overrun has happened. appropriate actions may be taken (i.e. discarding the capture register value etc.). 5. go to 3. 5.14.4. inactivation the capcom module is inactivated and returned to standby mode (power down mode) by setting the enable bit to 0. section 5.14.2. applies. ccxi and ccxm are only reset by system reset, not by standby mode.
preliminary data sheet vct 38xxa/b micronas 125 5.14.5. capcom registers the capcom module counter has to be read low byte first to avoid inconsistencies. csf clock selection field w: source of ccc clock (see table 5 ? 10) table 5 ? 10: csf usage msk mask flag w1: enable. w0: disable. these mask flags refer to the corresponding event flags in capcom interrupt register. fol force output action logic r/w1: force output action logic. r/w0: release output action logic. this flag is static. as long as fol is true neither com- parator can trigger nor sw can force, by writing another ? one ? , the output action logic. after forcing it is recommended to clear fol unless output action logic should not be locked. oam output action mode r/w: defines behavior of output action logic. iam input action mode r/w: defines behavior of input action logic. 226: 1f7c 227: cccl 228: capcom counter low byte bit76543210 r read low byte and lock ccc. reset00000000 229: 1f7d 230: ccch 231: capcom counter high byte bit76543210 r read high byte and unlock ccc. reset00000000 232: 1f14 233: cccs 234: capcom clock select bit76543210 w csf reset00000000 csf clock divider timer clock timer increment timer period 00 f osc /2 0 10.125 mhz 98.765 ns 6.4727 ms 01 f osc /2 4 632.81 khz 1.5802 s 103.56 ms 10 f osc /2 8 39.551 khz 25.284 s 1.6570 s 11 f osc /2 12 2.4719 khz 404.54 s 26.512 s 235: 1f6c 236: cc0m 237: capcom 0 mode register 238: 1f70 239: cc1m 240: capcom 1 mode register bit76543210 r msk msk msk fol oam iam reset00000000 table 5 ? 11: oam usage oam output action logic modes 0 0 disabled, ignore trigger, output low level. 0 1 toggle output. 1 0 output low level. 1 1 output high level. table 5 ? 12: iam usag e iam input action logic modes 0 0 disabled, don ? t trigger. 0 1 trigger on rising edge. 1 0 trigger on falling edge. 1 1 trigger on rising and falling edge.
vct 38xxa/b preliminary data sheet 126 micronas cap capture event r1: event. r0: no event. w1: clear flag. cmp compare event r1: event. r0: no event. w1: clear flag. ovl overflow event r1: event. r0: no event. w1: clear flag. lac lock after capture r/w1: enable. r/w0: disable. rcr reset capture register r/w1: reset capture register to ffffh. r/w0: release capture register. ccsipn capcom special input port n this field defines the special input port connected to the associated su (see table on page 137). 241: 1f6d 242: cc0i 243: capcom 0 interrupt register 244: 1f71 245: cc1i 246: capcom 1 interrupt register bit76543210 r/w cap cmp ofl lac rcr x x x reset00000000 247: 1f6e 248: cc0l 249: capcom 0 capture/compare low byte 250: 1f72 251: cc1l 252: capcom 1 capture/compare low byte bit76543210 r read low byte of capture register and lock it. w write low byte of compare register and lock it. reset11111111 253: 1f6f 254: cc0h 255: capcom 0 capture/compare high byte 256: 1f73 257: cc1h 258: capcom 1 capture/compare high byte bit76543210 r read high byte of capture register and unlock it. w write high byte of compare register and unlock it. reset11111111 259: 1e70 260: ccimux 261: capcom input multiplex register bit76543210 w ccsip1 ccsip0 reset00000000
preliminary data sheet vct 38xxa/b micronas 127 5.15. pulse width modulator each of the 4 available pwms is an 8-bit reload down- counter with fixed reload interval. it serves to generate a frequency signal with variable pulse width or, with an external low-pass filter, as a digital to analog con- verter. 5.15.1. features ? 8-bit resolution ? standby mode 5.15.2. general a pwm ? s 8-bit down-counter is clocked by its input clock and counts down to zero. reaching zero, it stops and sets the output to low. a load pulse reloads the counter with the content of the pwm register, restarts it and sets the output to high. the repetition rate is 19.775 khz, the reload period is 50.57 s. the pwms are not affected by cpu slow mode. it is recommended that the cpu should not write the pwm registers during slow mode. 5.15.3. initialization prior to entering active mode, proper sw initialization of the ports assigned to function as pwmx outputs has to be made. the ports have to be configured special out (see section 5.19. on page 137). 5.15.4. operation after reset, all pwms are in standby mode (inactive) and the output signal pwmx is low. for entering active mode, the enable bit in the corre- sponding standby register has to be set (see section 5.5. on page 93). the desired pulse width value is then written into register pwmx. each pwm will start producing its output signal immediately after the next subsequent load pulse. during active mode, a new pulse width value is set by simply writing to the register pwmx. upon the next subsequent load pulse the pwm will start producing an output signal with the new pulse width value, start- ing with a high level. returning a pwm to standby mode by resetting its respective enable flag will immediately set its output low. the state of the down-counters is not readable. 5.15.5. pwm registers fig. 5 ? 24: block diagram of 8-bit pwm 262: 1f50 263: pwm0 264: pwm 0 register 265: 1f51 266: pwm1 267: pwm 1 register 268: 1f52 269: pwm2 270: pwm 2 register 271: 1f53 272: pwm3 273: pwm 3 register bit76543210 w pulse width value reset00000000 table 5 ? 13: pulse width programming pulse width value pulse duty factor 00h 0% (output is static low) 01h 1/256 02h 2/256 :: feh 254/256 ffh 100% (output is static high) 1) 1 ) pulse duty factor 255/256 is not selectable. x: pwm number 0 to 3 y: standby register 0 or 2 8 zero pulse width register pwmx w clk sq r 1 0 load 8-bit down counter 1 0 sry.pwmx pwmx 1 0 f osc /2 1 f osc /2 9
vct 38xxa/b preliminary data sheet 128 micronas 5.16. tuning voltage pulse width modulator the tuning voltage pulse width modulator (tvpwm), in combination with an external low pass filter, serves as a digital to analog converter to control voltage syn- thesis tuning. it can also be operated as a normal 8-bit pwm. 5.16.1. features ? 14bit resolution ? standby mode 5.16.2. general the tvpwm is based on an 8-bit pwm built by a counter and a programmable comparator (see fig. 5 ? 26). the overflow of the counter reloads the compara- tor with the content of the tvpwmh register and sets the tvpwm output to high. matching the counter value, the comparator sets the tvpwm output to low. the counter is continually running, producing pwm cycles with a length of 256 t. depending on the content of the tvpwml register, the 6-bit pulse extension logic will add additional single clock pulses distributed over a frame of 64 reload cycles (see fig. 5 ? 25). this gives 14-bit resolution when integrating over a complete frame. the frame rate is 309 hz, the frame period is 3.24 ms. an interrupt is generated after completion of a frame of 64 reload cycles. the interrupt source output of this module is routed to the interrupt controller logic (see section 5.10. on page 104). the tvpwm is not affected by cpu slow mode. it is recommended that the cpu should not write the tvpwm registers during slow mode. fig. 5 ? 25: tvpwm timing fig. 5 ? 26: block diagram of 14bit tuning voltage pwm cycle n cycle n+1 256 t 256 t 1 t tvpwml register 8 tvpwmh register w clk 1 0 8 bit pwm counter sr0.tvpwm tvpwm f osc /2 1 6 1 tvpwm interrupt source 6 bit frame counter load comparator extension logic pwm pulse 86
preliminary data sheet vct 38xxa/b micronas 129 5.16.3. initialization prior to entering active mode, proper sw initialization of the ports assigned to function as tvpwm output has to be made. the ports have to be configured spe- cial out (see section 5.19. on page 137). 5.16.4. operation after reset, the tvpwm is in standby mode (inactive) and the output signal tvpwm is low. for entering active mode, the enable bit in the corre- sponding standby register has to be set (see section 5.5. on page 93). the desired pulse width value is then written into the registers tvpwml and tvp- wmh. the tvpwm will start producing its output sig- nal immediately after the next subsequent load pulse. during active mode, a new pulse width value is set by simply writing to the register tvpwml and tvpwmh. writing tvpwmh will update the comparator and the extension logic with the new register values. upon the next subsequent load pulse the tvpwm will start pro- ducing an output signal with the new pulse width value, starting with a high level. returning the tvpwm to standby mode by resetting its respective enable flag will not reset its output signal. the state of the counters and the extension logic is not readable. 5.16.5. tvpwm registers tvpwm has to be written low byte first. 274: 1f4a 275: tvpwml 276: tv pwm low byte bit76543210 w pulse width value low reset 000000 277: 1f4b 278: tvpwmh 279: tv pwm high byte bit76543210 w pulse width value high reset00000000
vct 38xxa/b preliminary data sheet 130 micronas 5.17. a/d converter (adc) this 10-bit analog to digital converter allows the con- version of an analog voltage in the range of 0 to vsup s into a digital value. a multiplexer connects the adc to one of 15 analog input ports. a sample-and- hold circuit holds the analog voltage during conver- sion. the duration of the sampling time is programma- ble. the a/d conversion is done by a charge balance a/d converter using successive approximation. 5.17.1. features ? a/d converter with 10-bit resolution. ? successive approximation, charge balance type. ? input multiplexer with 15 analog channels. ? sample and hold circuit. ? 4/8/16/32 s conversion selectable for optimum throughput/accuracy balance. ? zero standby current, 300 a active current. fig. 5 ? 27: block diagram of the adc p10-17 a d s&h x x x x tsamp channel ad0 ad1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 987 432 10 vsups 0 1 gnds 4 sr1.adc eoc cmpo cmpo 2 10 r w r 5 6 interrupt source mux 15 p20-26
preliminary data sheet vct 38xxa/b micronas 131 5.17.2. operation after reset, the module is off (zero standby current). the module is enabled by the flag sr1.adc. the user must ensure that the flag end of conversion (eoc) in register ad0 is true, before he starts to operate the module. a write access to register ad0 indicating sample time and channel number starts the conversion. the flag eoc signalizes the end of conversion. the 10-bit result is stored in the registers ad1 (8 msb) and ad0. the conversion rate depends on the software, the oscillator frequency and the programmed sample time. the adc module is not affected by cpu slow mode. 5.17.3. measurement errors the result of the conversion mirrors the voltage poten- tial of the sampling capacitance (typically 15 pf) at the end of the sampling time. this capacitance has to be charged by the source through the source impedance within the sampling time period. to avoid measure- ment errors, system design has to make sure that at the end of the sampling period, the potential error on the sampling capacitance is less than 0.1 lsb. measurement errors may occur, when the voltage of high-impedance sources has to be measured: ? to reduce these errors, the sampling time may be increased by programming the field tsamp in reg- ister ad1. ? in cases where high-impedance sources are only rarely sampled, a 100-nf capacitor from the input to gnds is a sufficient measure to ensure that the potential on the sampling capacitance reaches the full source potential, even with the shortest sam- pling time. ? in some high-impedance applications a charge pumping effect may influence the measurement result when two sources are measured alternatingly. 5.17.4. comparator in addition to the a/d converter the module contains a comparator. the level at the a/d converter input is compared to vsups/2. the state of the comparator output can be read at flag cmpo in register ad0. the interrupt source output of this module is routed to the interrupt controller logic. the cmpo interrupt source is gated with an internal clock. this is the rea- son why interrupts are generated as long as the level at the comparator is lower than the internal reference.
vct 38xxa/b preliminary data sheet 132 micronas 5.17.5. adc registers a write access to register ad0 starts the a/d conver- sion of the written channel number and sampling dura- tion. the flag eoc signals the end of conversion. the result is stored in register ad1 (bit 9 to 2) and in regis- ter ad0 (bit 1 and 0). eoc end of conversion r1: end of conversion r0: busy eoc is reset by a write access to the register ad0. eoc must be true before starting the first conversion after enabling the module by setting sr1.adc. cmpo comparator output r1: input is lower than reference voltage. r0: input is higher than reference voltage. tsamp sampling time tsamp adjusts the sample time and the conversion time. the total conversion time is 20 clock cycles longer than the sample time. sampling starts one clock cycle after completion of the write access to ad0. channel channel of input multiplexer channel selects from which port pin the conversion is done. the msb of channel is bit 3. no port pin is connected to the adc if the channel 0 is selected. in this case the input of the a/d converter is connected to ground. after reset, channel is set to zero. an 9 to 0 analog value bit 9 to 0 the 10 bit analog value is in the range of 0 to 1023. the 8 msb can be read from register ad1. the two lsb can be read from register ad0. the result is avail- able until a new conversion is started. 280: 1fa8 281: ad0 282: adc register 0 bit76543210 r eoccmpoxxxxan1an0 w tsamp channel reset00000000 283: 1fa9 284: ad1 285: adc register 1 bit76543210 r an9 an8 an7 an6 an5 an4 an3 an2 reset table 5 ? 14: sampling time adjustment tsamp t sample t conversion 0h 20 t osc 40 t osc 1h 60 t osc 80 t osc 2h 140 t osc 160 t osc 3h 300 t osc 320 t osc table 5 ? 15: adc input multiplexer channel port pin 0 none 1p10 2p11 3p12 4p13 5p14 6p15 7p16 8p17 9p20 10 p21 11 p22 12 p23 13 p24 14 p25 15 p26
preliminary data sheet vct 38xxa/b micronas 133 5.18. closed caption module (cc) the text slicer that is implemented in the tpu is mainly designed for teletext applications. other services as closed captioning or cgms data slicing are possible but only with limited performance. therefore the vct 38xxb includes a standalone closed caption & cgms decoder module. the module is connected to the luma adc of the video front-end and uses the complete sync slicing of the video front-end. the decoded information is made available to the cpu via a set of memory mapped registers. 5.18.1. features the decoder supports the following features: closed captioning (field 1&2) for us subtitling extended data services (xds): time of day, local time zone, program rating, ... cgms data: copyright info, aspect ratio, indication of protection with split-burst / pseudo-sync pulses automatic threshold adaption or programmable fix threshold fig. 5 ? 28: block diagram of closed caption module timing lpf threshold adaption bitslicing timing recovery shift register formatter control register hsync vsync interlace yin interface
vct 38xxa/b preliminary data sheet 134 micronas 5.18.2. operation 5.18.2.1. lowpass filter the incoming video signal is bandlimited to f g =1 mhz to improve the performance with noisy signals. 5.18.2.2. input timing a timing unit generates a horizontal and vertical time- base that is synchronized to the video timing. the nominal delay between horizontal sync and the begin of the clock run-in (cri) of the caption line is specified to 10.5 us. the window in which the cri is detected can be shifted with a programmable 6bit hori- zontal offset. the generated vertical timing can be shifted as well with a programmable vertical offset by +/- 7 lines. additionally for the second field an offset of +/- 1 line can be selected. depending on the active mode, the timing unit gener- ates several enable signals to allow caption & cgms processing. the possible modes are: closed caption, line 21, 1st field only closed caption, line 21, 2nd field only closed caption, line 21, both fields cgms, line 20, both fields note that all modes can be combined also. 5.18.2.3. threshold adaption if caption data is present, the amplitude of the cri is measured during a fix window with a length of 80 cycles. this corresponds to 2 complete periods of the cri frequency. this result is used as adaptive thresh- old for the bitslicing. if no caption data is present, the default or the last measured value is used. the last value is stored and can be read by the cpu. alterna- tively a fix value can be programmed by the cpu. for cgms data, the adaptive or fix threshold can be selected independently. in both cases the correspond- ing value for captioning is used, but is rescaled for cgms by a factor of 1.4 as the nominal amplitude of caption data is 50 ire and that of cgms data is 70 ire. to avoid that in the case of a wrong measurement the adaptive threshold lies completely below or above the signal range, it is ? pseudo ? limited to a range of approx- imately 50..150% of the default level. this pseudo-limi- tation is done by forcing the msbs to a certain range and thus remapping forbidden ranges into the allowed region. 5.18.2.4. bitslicing the incoming video signal is compared to the currently valid threshold. the result of this hard decision is used for the bit timing recovery. resampled with the bit tim- ing it leads to the final result of the slicing process. 5.18.2.5. timing recovery the bit timing is recovered by a digital pll using a 15 bit accumulator. this accu is incremented with a con- stant value thus generating a fix frequency. the detected edges in the bitstream are used for an update of the phase. for captioning the phase error at the edges is measured and corrected proportionally depending on a programmable gain. during the cri the accu has the same frequency but generates twice as much sample pulses. for captioning the phase errors during a line are accumulated to allow the calcu- lation of the ideal startphase at the begin of a line. this value is used in the next field. for cgms the phase correction only consists of a hard reset at each edge. an adaption of the startphase is not necessary in this case. 5.18.2.6. shift register with the sample pulses generated by the timing recov- ery, the shift register latches the actual bit. it stores the last 8 received bits. when a complete byte has been received, it is moved into the corresponding data regis- ter in the output formatter. 5.18.2.7. controlling after the reception of each byte, the control unit gener- ates a latch pulse for the output formatter. when all bytes have been received the status information is updated to indicate that new data is available. 5.18.2.8. formatter the formatter latches all received bytes into the corre- sponding output register. in total there are 6 registers: ? caption status + cgms status (can be used optionally) ? 1st caption byte ? 2nd caption byte ? cgms status + cgms bit[4:1] ? cgms bit[12:5] ? cgms bit[20:13] if the data register is not read before the next byte is received, an overflow bit is set in the status register.
preliminary data sheet vct 38xxa/b micronas 135 5.18.3. ccm registers encc enable closed caption w0: disable caption acquisition w1: enable caption acquisition in line 21 fscc field select closed caption w00: enable field 1 acquisition w01: enable field 2 acquisition w1x: enable field 1+2 acquisition eftcc enable fix threshold closed caption w0: enable adaptive threshold w1: enable fix threshold rof reset overflow flags w0: no action w1: reset overflow flags in status register encgms enable cgms w0: disable cgms acquisition w1: enable cgms acquisition in line 20 scgms short cgms mode w0: receive full 20bit cgms data w1: receive only first 4bit cgms data eftcgms enable fix threshold cgms w0: enable adaptive threshold w1: enable fix threshold pgain phase gain w00: low w11: high fldoffs 2nd field offset w00: 0 line offset to 1st field w01: +1 line offset to 1st field w10: -2 line offset to 1st field w11: -1 line offset to 1st field dv data valid r0: data invalid r1: data valid fid field id r0: currently available data from field 1 r1: currently available data from field 2 oo overflow occured r0: no overflow of data buffer r1: overflow of data buffer 286: 1eb0 287: ccm1 288: cc mode 1 bit76543210 r/w rof eftcc fscc encc reset00000000 289: 1eb1 290: ccm2 291: cc mode 2 bit76543210 r/w eftcgm s scgms encgms reset00000000 292: 1eb2 293: cchtim 294: cc horizontal timing bit76543210 r/w pgain horizontal offset -32..+31 (in steps of 0.4us) reset10000000 295: 1eb3 296: ccvtim 297: cc vertical timing bit76543210 r/w fldoffs vertical offset -32..+31 reset00000000 298: 1eb4 299: ccthr 300: cc threshold bit76543210 r adaptive threshold 0..255 w fix threshold 0..255 reset00000000 301: 1eb6 302: ccstat 303: cc status bit76543210 cgmsstat ccstat r oo fid dv oo fid dv reset00000000
vct 38xxa/b preliminary data sheet 136 micronas 304: 1eb7 305: ccb1 306: cc byte 1 bit76543210 r cc byte 1 reset00000000 307: 1eb8 308: ccb2 309: cc byte 2 bit76543210 r cc byte 2 reset00000000 310: 1eb9 311: cgms1 312: cc cgms 1 bit76543210 cgmsstat r cgms bit 4-1 oo fid dv 00000000 313: 1eba 314: cgms2 315: cc cgms 2 bit76543210 r cgms bit 12-5 reset00000000 316: 1ebb 317: cgms3 318: cc cgms 3 bit76543210 r cgms bit 20-13 reset00000000
preliminary data sheet vct 38xxa/b micronas 137 5.19. ports there exist different kinds of ports. the universal ports, p1 to p3, serve as digital i/o and have addi- tional special input and output functions. a subset of the universal ports (p10-p17, p20-p26) serves as input for the analog-to-digital converter. the i 2 c ports sda, scl can alternatively be used as digital i/o ports. the analog audio ports ain1 ? 3, aout1 ? 2 can alternatively be used as digital input ports. the 20.25 mhz system clock output clk20 can alterna- tively be used as digital output port. 5.19.1. port assignment table 5 ? 17 shows the assignment of port pins to spe- cial input and output functions. every special output function is connected to 2 port pins in parallel and can be activated via the mod flag in the corresponding port register. the adc input multiplexer can be connected to 1 of 15 port pins. the output driver of the selected port pin is then forced to open-drain mode. additionally it can be disabled using the en flag in the corresponding port register. every special input function can be connected to 1 of 15 input ports (see table 5 ? 16). if port number 0 is selected the special input function is connected to ground. changing the input port may produce tempo- rary glitch signals. therefore, the corresponding spe- cial input function should be disabled before the input port is changed. table 5 ? 16: special input configuration special input number special input function special input port 1 cc0 ? in 0 ? 15 2 cc1 ? in 0 ? 15 3pint00 ? 15 4pint10 ? 15 5pint20 ? 15 6pint30 ? 15 table 5 ? 17: port pin configuration port name adc input special output special input port p10 1 timer 0 1 p11 2 timer 1 2 p12 3 cc0 ? out 3 p13 4 cc1 ? out 4 p14 5 tvpwm 5 p15 6 pwm 0 6 p16 7 pwm 1 7 p17 8 pwm 2 8 p20 9 pwm 3 9 p21 10 clk20 10 p22 11 sda 2 11 p23 12 scl 2 12 p24 13 timer 0 p25 14 timer 1 p26 15 cc0 ? out p27 cc1 ? out p30 tvpwm p31 pwm 0 p32 pwm 1 p33 pwm 2 p34 pwm 3 p35 clk20 p36 sda 2 p37 scl 2 p40 sda p41 scl p42 aout1 p43 aout2 13 p44 ain1 p45 ain2 14 p46 ain3 15
vct 38xxa/b preliminary data sheet 138 micronas 5.19.2. universal ports p1 to p3 there are 24 universal port pins. the universal ports p1 to p3 are each 8 bits wide. in the 64-pin psdip package only 12 universal port pins are available (p10 ? p17, p20 ? p23). 5.19.2.1. features ? digital i/o port ? special input and output function ? analog input function ? schmitt trigger input buffer ? tristate output ? push-pull or open-drain output ? 10-ma output current ? output supply either 3.3 v or 5.0 v fig. 5 ? 29: universal port circuit universal ports can be operated in different modes. after reset, all universal ports are in normal mode, tristate condition. d q d q d q 0 1 px.y dby special in x.y special out x.y pxe pxm pxd write pxd read x: port number 1 to 3 y: port pin number 0 to 7 adc in x.y v dd v ss pxv dd pxv ss d q pxo table 5 ? 18: universal ports operating modes modes function port mode normal input the sw uses the ports as digital input. special input the port input is additionally connected to specific hardware modules. normal output the sw uses the ports as latched digital tristate output. special output the port output is directly driven by specific hardware modules.
preliminary data sheet vct 38xxa/b micronas 139 5.19.2.2. universal port mode each port bit can be individually configured to several port modes. the output driver of each pin has to be enabled by setting the en flag. using the out flag the output stage can be configured to either open drain or push pull output. the mod flag selects the source of the output value. the special input mode is always active. this allows manipulating the input signal to the special hardware through normal output operations by software. as the special output mode allows reading the pin lev- els, the output state of the special hardware may be read by the cpu. 5.19.3. universal port registers universal port data registers pxd contain input/output data of the corresponding port. the ? x ? in pxd means the number of the port. thus pxd stands for p1d to p3d. d0 ? 7 universal port data input/output r: read pin level resp. data latch. w: write data to data latch. to use a port pin as software output, the appropriate driver must be activated by setting the en flag and the mod flag must be programmed to normal mode. out0 ? 7 output flag w1: output driver is open drain w0: output driver is push pull mod0 ? 7 normal/special mode flag w1: special output mode w0: normal output mode the mod flag defines from which source the pin is driven if the en flag is true. en0 ? 7 enable flag w1: output driver is enabled w0: output driver is disabled table 5 ? 19: port mode register settings mode mod en d function normal input x 0 x read of register pxd returns port pin input levels to data bus. normal output 0 1 data write to register pxd changes level of port pin output drivers. read of register pxd returns the pxd register set- ting to the data bus. special input x x x port pin input level is presented to special hardware. special output 1 1 x special hardware drives port pin. read of register pxd returns port pin input levels to data bus. 319: 1f90 320: p1d 321: port 1 data register 322: 1f94 323: p2d 324: port 2 data register 325: 1f98 326: p3d 327: port 3 data register bit76543210 r/w d7 d6 d5 d4 d3 d2 d1 d0 reset00000000 328: 1f91 329: p1o 330: port 1 output register 331: 1f95 332: p2o 333: port 2 output register 334: 1f99 335: p3o 336: port 3 output register bit76543210 w out7 out6 out5 out4 out3 out2 out1 out0 reset00000000 337: 1f92 338: p1m 339: port 1 mode register 340: 1f96 341: p2m 342: port 2 mode register 343: 1f9a 344: p3m 345: port 3 mode register bit76543210 w mod7 mod6 mod5 mod4 mod3 mod2 mod1 mod0 reset00000000 346: 1f93 347: p1e 348: port 1 enable register 349: 1f97 350: p2e 351: port 2 enable register 352: 1f9b 353: p3e 354: port 3 enable register bit76543210 w en7 en6 en5 en4 en3 en2 en1 en0 reset00000000
vct 38xxa/b preliminary data sheet 140 micronas 5.19.4. i 2 c ports p40 and p41 the i 2 c ports sda and scl can alternatively be used as digital i/o ports. to activate the i 2 c function of the port pin the corresponding mod flag has to be set to special mode. in normal mode the port pin serves as digital i/o. the output stage is open-drain only. after reset, the i 2 c ports are in special mode. 5.19.4.1. features ? digital i/o port ? i 2 c input and output function ? schmitt trigger input buffer ? open-drain output ? connected to standby supply scld scl data input/output r: read pin level resp. data latch. w: write data to data latch. sdad sda data input/output r: read pin level resp. data latch. w: write data to data latch. to use the i 2 c ports as software output, the appropri- ate drivers must be activated by setting the sclen and sdaen flag and resetting the sclm and sdam flags. sclm scl normal/special mode flag w1: special i2c output mode w0: normal output mode sdam sda normal/special mode flag w1: special i2c output mode w0: normal output mode sclen scl enable flag w1: output driver is enabled w0: output driver is disabled sdaen sda enable flag w1: output driver is enabled w0: output driver is disabled fig. 5 ? 30: i 2 c port circuit 355: 1f9c 356: p4d 357: port 4 data register bit76543210 r ain3d ain2d ain1d aout2d aout1d scld sdad w scld sdad reset 0000000 358: 1f9e 359: p4m 360: port 4 mode register bit76543210 w ain3m ain2m ain1m aout2m aout1m sclm sdam reset 1110011 361: 1f9f 362: p4e 363: port 4 enable register bit76543210 w sclen sdaen reset 1 1 d q d q d q 0 1 p40 db0/db1 sda/scl in sda/scl out p4e p4m p4d write p4d read v dd v ss v dd v ss p41 0 1
preliminary data sheet vct 38xxa/b micronas 141 5.19.5. audio ports p42 to p46 the analog audio ports ain1 ? 3, aout1 ? 2 can alter- natively be used as digital input ports. to activate the audio function of the port pin, the corresponding mod flag has to be set to special mode. in normal mode the port pin serves as digital input. after reset the audio output ports are in normal mode, the audio input ports are in audio mode. 5.19.5.1. features ? analog audio input or output ? digital input port ? schmitt trigger input buffer ? special input function mod flags ainxd ainx data input r: read pin level resp. data latch. aoutxd aoutx data input r: read pin level resp. data latch. to use the audio ports as software input, the corre- sponding flags must be programmed to normal input mode. ainxm ainx normal/special mode flag w1: special audio input mode w0: normal input mode aoutxm aoutx normal/special mode flag w1: special audio output mode w0: normal input mode fig. 5 ? 31: audio port circuit d q 0 1 p4.y dby special in 4.y p4m p4d read y: port pin number 2 to 6 audio v dd v ss
vct 38xxa/b preliminary data sheet 142 micronas 5.19.6. clk20 output port the clk20 pin delivers the internal 20.25-mhz clock. the output stage is push-pull with programmable driver strength (c20m.dstr). the clk20 pin can alternatively be used as digital output port. it is possi- ble to force the clk20 output either to high or low (c20m.fso) or to switch it into tristate mode (c20m.dod). after reset, the clk20 port is enabled. 5.19.6.1. features ? programmable driver strength ? tristate mode ? digital output port dstr driver strength w000: output driver strong w111: output driver weak dod disable output driver w1: output driver is high-impedance w0: output driver is enabled fso force static output w10: output driver is forced to 1 w11: output driver is forced to 0 fig. 5 ? 32: clk20 port circuit 364: 1f9d 365: c20m 366: clk20 mode register bit76543210 w fso dod dstr reset 0000000 clk20 c20m v dd v ss clk20 db 6
preliminary data sheet vct 38xxa/b micronas 143 5.20. i/o register cross reference table 5 ? 20: i/o register map addr. mnemonic name mode reset section 1e00 mask1l mask 1 low byte w ff dma interface (chapter 5.9. on page 101) 1e01 mask2l mask 2 low byte w ff 1e02 mask3l mask 3 low byte w ff 1e03 mask4l mask 4 low byte w ff 1e04 mask1h mask 1 high byte w ff 1e05 mask2h mask 2 high byte w ff 1e06 mask3h mask 3 high byte w ff 1e07 mask4h mask 4 high byte w ff 1e08 cmp1l compare 1 low byte w ff 1e09 cmp2l compare 2 low byte w ff 1e0a cmp3l compare 3 low byte w ff 1e0b cmp4l compare 4 low byte w ff 1e0c cmp1h compare 1 high byte w ff 1e0d cmp2h compare 2 high byte w ff 1e0e cmp3h compare 3 high byte w ff 1e0f cmp4h compare 4 high byte w ff 1e10 map1l map 1 low byte w ff 1e11 map2l map 2 low byte w ff 1e12 map3l map 3 low byte w ff 1e13 map4l map 4 low byte w ff 1e14 map1h map 1 high byte w ff 1e15 map2h map 2 high byte w ff 1e16 map3h map 3 high byte w ff 1e17 map4h map 4 high byte w ff 1e18 dmaim dma interface mode w 00 1e64 par0 patch address register 0 w ff memory patch module (chapter 5.11. on page 114) 1e65 par1 patch address register 1 w ff 1e66 par2 patch address register 2 w ff 1e67 pdr patch data register w 00 1e68 per0 patch enable register 0 w 00 1e69 per1 patch enable register 1 w 00
vct 38xxa/b preliminary data sheet 144 micronas 1eb0 ccm1 cc mode 1 r/w 00 closed caption module (cc) (chapter 5.18. on page 133) 1eb1 ccm2 cc mode 2 r/w 00 1eb2 cchtim cc horizontal timing r/w 80 1eb3 ccvtim cc vertical timing r/w 00 1eb4 ccthr cc threshold r/w 00 1eb6 ccstat cc status r 00 1eb7 ccb1 cc byte 1 r 00 1eb8 ccb2 cc byte 2 r 00 1eb9 cgms1 cc cgms 1 r 00 1eba cgms2 cc cgms 2 r 00 1ebb cgms3 cc cgms 3 r 00 1f01 cr control register r/w ? control register (chap- ter 5.4. on page 91) 1f0f br banking register r/w 01 memory banking (chap- ter 5.8. on page 99) 1f00 csw0 clock, supply & watchdog register 0 w 01 reset logic (chapter 5.7. on page 95) 1f60 csw1 clock, supply & watchdog register 1 r/w ff 1f07 rc reset control register r/w 00 1f08 sr0 standby register 0 r/w 00 standby registers (chapter 5.5. on page 93) 1f09 sr1 standby register 1 r/w 40 1f0a sr2 standby register 2 r/w 00 1fd0 i2cws0 i2c write start register 0 w 00 i2c-bus master inter- face (chapter 5.12. on page 116) 1fd1 i2cws1 i2c write start register 1 w 00 1fd2 i2cwd0 i2c write data register 0 w 00 1fd3 i2cwd1 i2c write data register 1 w 00 1fd4 i2cwp0 i2c write stop register 0 w 00 1fd5 i2cwp1 i2c write stop register 1 w 00 1fd6 i2crd i2c read data register r 00 1fd7 i2crs i2c read status register r 00 1fdb i2cm i2c mode register w 02 1e73 i2cps i2c port select register w 00 table 5 ? 20: i/o register map addr. mnemonic name mode reset section
preliminary data sheet vct 38xxa/b micronas 145 1f20 irc interrupt control register r/w 0c interrupt controller (chapter 5.10. on page 104) 1f21 irret interrupt return register r/w 00 1f22 irpri10 interrupt priority register, input 0 and 1 r/w 00 1f23 irpri32 interrupt priority register, input 2 and 3 r/w 00 1f24 irpri54 interrupt priority register, input 4 and 5 r/w 00 1f25 irpri76 interrupt priority register, input 6 and 7 r/w 00 1f26 irpri98 interrupt priority register, input 8 and 9 r/w 00 1f27 irpriba interrupt priority register, input 10 and 11 r/w 00 1f28 irpridc interrupt priority register, input 12 and 13 r/w 00 1f29 irprife interrupt priority register, input 14 and 15 r/w 00 1f2a irp interrupt pending register r 00 1f2b irpm0 interrupt port mode w 00 1f2c irpp interrupt port prescaler w 00 1e71 irpmux0 interrupt port multiplex 0 w 00 1e72 irpmux1 interrupt port multiplex 1 w 00 1fa8 ad0 adc register 0 r/w 00 a/d converter (adc) (chapter 5.17. on page 130) 1fa9 ad1 adc register 1 r 00 1f4e tim0l timer 0 low byte r/w ff timer t0 and t1 (chap- ter 5.13. on page 120) 1f4f tim0h timer 0 high byte r/w ff 1f11 tim0m timer 0 mode w 00 1f4c tim1l timer 1 low byte r/w ff 1f4d tim1h timer 1 high byte r/w ff 1f13 tim1m timer 1 mode w 00 1f4a tvpwml tv pwm low byte w 00 pulse width modulator (chapter 5.15. on page 127) 1f4b tvpwmh tv pwm high byte w 00 1f50 pwm0 pwm 0 register w 00 1f51 pwm1 pwm 1 register w 00 1f52 pwm2 pwm 2 register w 00 1f53 pwm3 pwm 3 register w 00 table 5 ? 20: i/o register map addr. mnemonic name mode reset section
vct 38xxa/b preliminary data sheet 146 micronas 1f6c cc0m capcom 0 mode register r/w 00 capture compare mod- ule (capcom) (chapter 5.14. on page 122) 1f6d cc0i capcom 0 interrupt register r/w 00 1f6e cc0l capcom 0 capture/compare low byte r/w ff 1f6f cc0h capcom 0 capture/compare high byte r/w ff 1f70 cc1m capcom 1 mode register r/w 00 1f71 cc1i capcom 1 interrupt register r/w 00 1f72 cc1l capcom 1 capture/compare low byte r/w ff 1f73 cc1h capcom 1 capture/compare high byte r/w ff 1f7c cccl capcom counter low byte r 00 1f7d ccch capcom counter high byte r 00 1f14 cccs capcom clock select w 00 1e70 ccimux capcom input multiplex register w 00 1f90 p1d port 1 data register r/w 00 ports (chapter 5.19. on page 137) 1f91 p1o port 1 output register w 00 1f92 p1m port 1 mode register w 00 1f93 p1e port 1 enable register w 00 1f94 p2d port 2 data register r/w 00 1f95 p2o port 2 output register w 00 1f96 p2m port 2 mode register w 00 1f97 p2e port 2 enable register w 00 1f98 p3d port 3 data register r/w 00 1f99 p3o port 3 output register w 00 1f9a p3m port 3 mode register w 00 1f9b p3e port 3 enable register w 00 1f9c p4d port 4 data register r/w 00 1f9e p4m port 4 mode register w 73 1f9f p4e port 4 enable register w 03 1f9d c20m clk20 mode register w 00 1ffb tst5 test register 5 r 00 test registers (chapter 5.6. on page 94) 1ffc tst4 test register 4 w 00 1ffd tst3 test register 3 w 00 1ffe tst1 test register 1 w 00 1fff tst2 test register 2 w 00 table 5 ? 20: i/o register map addr. mnemonic name mode reset section
preliminary data sheet vct 38xxa/b micronas 147 6. specifications 6.1. outline dimensions fig. 6 ? 1: 64-pin plastic shrink dual-inline package (psdip64) weight approximately 9.0 g dimensions in mm fig. 6 ? 2: 128-pin plastic metric quad flat package (pmqfp128) weight approximately 5.4 g dimensions in mm 132 33 64 57.7 0.1 0.8 0.2 3.8 0.1 3.2 0.2 1.778 1 0.05 31 x 1.778 = 55.1 0.1 0.48 0.06 20.3 0.5 0.28 0.06 18 0.05 19.3 0.1 spgs703000-1(p64)/1e 0.8 97 128 32 33 96 1 64 65 0.8 0.1 spgs706000-5(p128)/1e 31.2 0.1 31.2 0.1 0.17 0.06 3.775 0.325 0.34 0.05 3.4 0.2 28 0.1 28 0.1 31 x 0.8 = 24.8 0.1 31 x 0.8 = 24.8 0.1
vct 38xxa/b preliminary data sheet 148 micronas 6.2. pin connections and short descriptions nc = not connected lv = if not used, leave vacant x = obligatory; connect as described in circuit diagram in = input out = output supply = supply pin pin no. pin name type connection short description psdip 64-pin pmqfp 128-pin cpga 257-pin (if not used) 1 33 a-1 p17 in/out lv port 1, bit 7 2 34 c-2 p16 in/out lv port 1, bit 6 337c-1vsup p1 supply x supply voltage, port 1 438e-2gnd p1 supply x ground, port 1 5 35 b-1 p15 in/out lv port 1, bit 5 6 36 d-2 p14 in/out lv port 1, bit 4 7 39 d-1 p13 in/out lv port 1, bit 3 8 40 f-2 p12 in/out lv port 1, bit 2 9 41 e-1 p11 in/out lv port 1, bit 1 10 42 g-2 p10 / vin5 in/out lv port 1, bit 0 / analog video 5 input (vct 38xxb only!) 11 43 f-1 vout out lv analog video output 12 44 h-2 vrt in x reference voltage top, video adc 13 45 g-1 sgnd in gnd af signal ground for analog input 14 46 h-1 gnd af supply x ground, analog front-end 15 47 j-1 vsup af supply x supply voltage, analog front-end 16 48 k-1 cbin in vrt analog component cb input 17 49 l-1 cin1 in vrt analog chroma 1 input 18 50 m-1 cin2/ crin in vrt analog chroma 2 input / analog component cr input 19 51 n-1 vin1 in vrt analog video 1 input 20 52 n-2 vin2 in vrt analog video 2 input 21 53 p-1 vin3 in vrt analog video 3 input 22 54 p-2 vin4 in vrt analog video 4 input 23 89 y-16 test in gnd s test pin, reserved for test 24 76 w-8 hout out x horizontal drive output 25 77 y-7 vsup d supply x supply voltage, digital circuitry 26 78 y-8 gnd d supply x ground, digital circuitry 27 90 w-16 fblin in gnd ab fast blank input 28 91 y-17 rin in gnd ab analog red input
preliminary data sheet vct 38xxa/b micronas 149 29 92 w-17 gin in gnd ab analog green input 30 93 y-18 bin in gnd ab analog blue input 31 94 w-18 vprot in gnd d vertical protection input 32 95 y-19 safety in gnd d safety input 33 96 w-19 hflb in hout horizontal flyback input 34 97 y-20 vertq / intlc out lv differential vertical sawtooth output interlace control output 35 98 v-19 vert out lv differential vertical sawtooth output 36 99 w-20 ew out lv vertical parabola output 37 100 u-19 sense in gnd ab sense adc input 38 101 v-20 gndm supply x ground, madc input 39 102 t-19 rsw1 out lv range switch1 for measurement adc 40 103 u-20 rsw2 out lv range switch2 for measurement adc 41 104 r-19 svmout out vsup ab scan velocity modulation output 42 105 t-20 rout out vsup ab analog red output 43 106 p-19 gout out vsup ab analog green output 44 107 r-20 bout out vsup ab analog blue output 45 108 n-19 vsup ab supply x supply voltage, analog back-end 46 109 p-20 gnd ab supply x ground, analog back-end 47 110 n-20 vrd in x dac reference 48 111 m-20 xref in x reference input for rgb dacs 49 112 l-20 ain3 in gnd s analog audio 3input 50 113 k-20 ain2 in gnd s analog audio 2input 51 114 j-20 ain1 in gnd s analog audio 1 input 52 115 h-20 aout2 out lv analog audio 2 output 53 116 h-19 aout1 out lv analog audio 1 output 54 122 e-19 vsup s supply x supply voltage, standby 55 123 d-20 gnd s supply x ground, standby 56 120 f-19 xtal1 in x analog crystal input 57 121 e-20 xtal2 out x analog crystal output 58 117 g-20 resq in/out x reset input/output, active low 59 118 g-19 scl in/out x i 2 c bus clock 60 119 f-20 sda in/out x i 2 c bus data 61 62 v-2 p23 in/out lv port 2, bit 3 pin no. pin name type connection short description psdip 64-pin pmqfp 128-pin cpga 257-pin (if not used)
vct 38xxa/b preliminary data sheet 150 micronas 62 63 w-1 p22 in/out lv port 2, bit 2 63 64 w-2 p21 in/out lv port 2, bit 1 64 65 y-1 p20 in/out lv port 2, bit 0 1 a-20 adb17 out lv address bus 17 2b-18vsup adb supply x supply voltage, address bus 3a-19gnd adb supply x ground, address bus 4 b-17 adb16 out lv address bus 16 5 a-18 adb15 out lv address bus 15 6 b-16 adb14 out lv address bus 14 7 a-17 adb13 out lv address bus 13 8 b-15 adb12 out lv address bus 12 9a-16adb11 outlv address bus 11 10 b-14 adb10 out lv address bus 10 11 a-15 adb9 out lv address bus 9 12 b-13 adb8 out lv address bus 8 13 a-14 adb7 out lv address bus 7 14 a-13 adb6 out lv address bus 6 15 a-12 adb5 out lv address bus 5 16 a-11 vsup adb supply x supply voltage, address bus 17 a-10 gnd adb supply x ground, address bus 18 a-9 adb4 out lv address bus 4 19 a-8 adb3 out lv address bus 3 20 b-8 adb2 out lv address bus 2 21 a-7 adb1 out lv address bus 1 22 b-7 adb0 out lv address bus 0 23 a-6 db0 in/out lv data bus 0 24 b-6 db1 in/out lv data bus 1 25 a-5 db2 in/out lv data bus 2 26 b-5 db3 in/out lv data bus 3 27 a-4 vsup db supply x supply voltage, data bus 28 b-4 gnd db supply x ground, data bus 29 a-3 db4 in/out lv data bus 4 30 b-3 db5 in/out lv data bus 5 31 a-2 db6 in/out lv data bus 6 pin no. pin name type connection short description psdip 64-pin pmqfp 128-pin cpga 257-pin (if not used)
preliminary data sheet vct 38xxa/b micronas 151 32 b-2 db7 in/out lv data bus 7 55 r-1 disintrom in x disable internal rom 56 r-2 p27 in/out lv port 2, bit 7 57 t-1 p26 in/out lv port 2, bit 6 58 t-2 p25 in/out lv port 2, bit 5 59 u-1 p24 in/out lv port 2, bit 4 60 u-2 vsup p2 supply x supply voltage, port 2 61 v-1 gnd p2 supply x ground, port 2 66 w-3 vbclk in gnd d video bus clock 67 y-2 vb7 in gnd d video bus 7 68 w-4 vb6 in gnd d video bus 6 69 y-3 vb5 in gnd d video bus 5 70 w-5 vb4 in gnd d video bus 4 / bond 0=16k text ram 71 y-4 vb3 in gnd d video bus 3 / bond 1=cti 72 w-6 vb2 in gnd d video bus 2 / bond 2=scaler 73 y-5 vb1 in gnd d video bus 1 / bond 3=comb filter 74 w-7 vb0 in gnd d video bus 0 / bond 4=vdp full/lite 75 y-6 clk20 out lv 20 mhz system clock output 79 y-9 p37 in/out lv port 3, bit 7 80 y-10 p36 in/out lv port 3, bit 6 81 y-11 p35 in/out lv port 3, bit 5 82 y-12 p34 in/out lv port 3, bit 4 83 y-13 vsup p3 supply x supply voltage, port 3 84 w-13 gnd p3 supply x ground, port 3 85 y-14 p33 in/out lv port 3, bit 3 86 w-14 p32 in/out lv port 3, bit 2 87 y-15 p31 in/out lv port 3, bit 1 88 w-15 p30 in/out lv port 3, bit 0 124 d-19 we1q out lv write enable output 1 125 c-20 we2q out lv write enable output 2 126 c-19 oe1q out lv output enable output 1 127 b-20 oe2q out lv output enable output 2 128 b-19 adb18 out lv address bus 18 pin no. pin name type connection short description psdip 64-pin pmqfp 128-pin cpga 257-pin (if not used)
vct 38xxa/b preliminary data sheet 152 micronas 6.3. pin descriptions for psdip64 package pin 1,2,5-10, p17 ? p10 ? i/o port (fig. 6 ? 27) these pins provide cpu controlled i/o ports. p10 can be configured as video input vin5 (fig. 6 ? 9) on vct 38xxb only! pin 3, vsupp1* ? supply voltage, port 1 driver this pin is used as supply for the i/o port 1 driver. pin 4, gndp1 * ? ground, port 1 driver this is the ground reference for the i/o port 1 driver. pin 11, vout ? analog video output (fig. 6 ? 12) the analog video signal that is selected for the main (luma, cvbs) adc is output at this pin. on vct 38xxb this pin can also deliver the sum of luma and chroma input signals (s-vhs). an emitter follower is required at this pin. pin 12, vrt ? reference voltage top (fig. 6 ? 13) via this pin, the reference voltage for the a/d converters is decoupled. the pin is connected with 10 f/47 nf to the signal ground pin. pin 13, sgnd ? signal gnd for analog input this is the high quality ground reference for the video input signals. pin 14, gndaf* ? ground, analog front-end this pin has to be connected to the analog ground. no supply current for the digital stages should flow through this line. pin 15, vsupaf* ? supply voltage, analog front-end this pin has to be connected to the analog supply volt- age. no supply current for the digital stages should flow through this line. pin 16,18, cbin,crin ? analog chroma component input (fig. 6 ? 11) these pins are used as the chroma component (cb, cr) inputs required for the analog yuv interface. the input signal must be ac-coupled. the crin pin can alternatively be used as the second svhs chroma input (cin2). pin 17,18, cin1,cin2 ? analog chroma input (fig. 6 ? 10) these are the analog chroma inputs. a s-vhs chroma signal is converted using the chroma (video 2) ad converter. a resistive divider is used to bias the input signal to the middle of the converter input range. the input signal must be ac-coupled. the cin2 pin can alternatively be used as the chroma component (cr) input required for the analog yuv interface. pins 19 ? 22, vin1 ? 4 ? analog video input (fig. 6 ? 9) these are the analog video inputs. a cvbs or s-vhs luma signal is converted using the luma (video 1) ad converter. the input signal must be ac-coupled. pin 23, test ? test input (fig. 6 ? 5) this pin enables factory test modes. for normal opera- tion, it must be connected to ground. pin 24, hout ? horizontal drive output (fig. 6 ? 16) this open drain output supplies the drive pulse for the horizontal output stage. the polarity and gating with the flyback pulse are selectable by software. pin 25, vsupd* ? supply voltage, digital circuitry pin 26, gndd* ? ground, digital circuitry this is the ground reference for the digital circuitry. pin 27, fblin ? fast blank input (fig. 6 ? 18) these pins are used to switch the rgb outputs to the external analog rgb inputs. the active level (low or high) can be selected by software. pin 28,29,30, rin, gin, bin ? analog rgb input (fig. 6 ? 14) these pins are used to insert an external analog rgb signal, e.g. from a scart connector which can by switched to the analog rgb outputs with the fast blank signal. the analog back-end provides separate bright- ness and contrast settings for the external analog rgb signals. pin 31, vprot ? vertical protection input (fig. 6 ? 17) in the event of a malfunction of the vertical deflection stage, the vertical protection circuitry prevents the pic- ture tube from burnig in. during vertical blanking, a sig- nal level of 2.5 v is sensed. if a negative edge cannot be detected, the rgb output signals are blanked. pin 32, safety ? safety input (fig. 6 ? 17) this is a three-level input. low level means normal function. at the medium level rgb output signals are blanked. at high level rgb output signals are blanked and horizontal drive is shut off. pin 33, hflb ? horizontal flyback input (fig. 6 ? 17) via this pin the horizontal flyback pulse is supplied to the vct 38xxa/b. pin 34, vertq, intlc ? inverted vertical sawtooth output (fig. 6 ? 20) / interlace output (fig. 6 ? 19) this pin supplies the inverted signal of vert. together with the vert pin it can be used to drive symmetrical deflection amplifiers. the drive signal is generated with 15-bit precision. the analog voltage is generated by a 4 bit current-dac with external resistor and uses digi- tal noise shaping. alternatively this pin supplies the interlace information, the polarity is programmable.
preliminary data sheet vct 38xxa/b micronas 153 pin 35, vert ? vertical sawtooth output (fig. 6 ? 20) this pin supplies the drive signal for the vertical output stage. the drive signal is generated with 15-bit preci- sion. the analog voltage is generated by a 4 bit cur- rent-dac with external resistor and uses digital noise shaping. pin 36, ew ? east-west parabola output (fig. 6 ? 21) this pin supplies the parabola signal for the east-west correction. the drive signal is generated with 15 bit precision. the analog voltage is generated by a 4 bit current-dac with external resistor and uses digital noise shaping. pin 37, sense ? measurement adc input (fig. 6 ? 23) this is the input of the analog to digital converter for the picture and tube measurement. three measure- ment ranges are selectable with rsw1 and rsw2. pin 38, gndm ? measurement adc reference input this is the ground reference for the measurement a/d converter. connect this pin to gnd ab pin 39, 40, rsw1 , rsw2 ? range switch for measur- ing adc (fig. 6 ? 22) these pins are open drain pull-down outputs. rsw1 is switched off during cutoff and whitedrive measure- ment. rsw2 is switched off during cutoff measure- ment only. pin 41, svmout ? scan velocity modulation output (fig. 6 ? 15) this output delivers the analog svm signal. the d/a converter is a current sink like the rgb d/a convert- ers. at zero signal the output current is 50% of the maximum output current. pin 42, 43, 44, rout, gout, bout ? analog rgb output (fig. 6 ? 15) these pins are the analog red/green/blue outputs of the back-end. the outputs are current sinks. pin 45, vsupab* ? supply voltage, analog back-end this pin has to be connected to the analog supply volt- age. no supply current for the digital stages should flow through this line. pin 46, gndab* ? ground, analog back-end this pin has to be connected to the analog ground. no supply current for the digital stages should flow through this line. pin 47, vrd ? dac reference decoupling (fig. 6 ? 24) via this pin the dac reference voltage is decoupled by an external capacitor. the dac output currents depend on this voltage, therefore a pull-down transis- tor can be used to shut off all beam currents. a decou- pling capacitor of 4.7 f in parallel to 100 nf (low inductance) is required. pin 48, xref ? dac current reference (fig. 6 ? 24) external reference resistor for dac output currents, typical 10 k ? to adjust the output current of the d/a converters. (see recommended operating conditions). this resistor has to be connected to analog ground as closely as possible to the pin. pin 49, 50, 51, ain1 ? 3 ? analog audio input (fig. 6 ? 25) the analog input signal from tuner or scart is fed to this pin. the input signal must be ac-coupled. alter- natively these pins can be used as digital input port (fig. 6 ? 25). pin 52, 53, aout1, aout2 ? analog audio output (fig. 6 ? 26) these pins are the analog audio outputs. connections to these pins must use a 680 ohm series resistor as closely as possible to these pins. the output signals are intended to be ac coupled. alternatively these pins can be used as digital input port (fig. 6 ? 26). pin 54, vsups* ? supply voltage, standby pin 55, gnds* ? ground, standby this is the ground reference for the standby circuitry. pins 56 and 57, xtal1 crystal input and xtal2 crys- tal output (fig. 6 ? 7) these pins are connected to an 20.25 mhz crystal oscillator which is digitally tuned by integrated shunt capacitances. the clk20 clock signal is derived from this oscillator. pin 58, resq ? reset input/output (fig. 6 ? 6) a low level on this pin resets the vct 38xxa/b. the internal cpu can pull down this pin to reset external devices connected to this pin. pin 59, scl ? i 2 c bus clock (fig. 6 ? 6) this pin connects to the i 2 c bus clock line. the signal can be pulled down by external slave ics to slow down data transfer. pin 60, sda ? i 2 c bus data (fig. 6 ? 6) this pin connects to the i 2 c bus data line. pin 61 ? 64, p20 ? p23 ? i/o port (fig. 6 ? 27) these pins provide cpu controlled i/o ports.
vct 38xxa/b preliminary data sheet 154 micronas 6.4. pin descriptions for pmqfp128 package pins 1, 4 ? 15, 18 ? 22, 128, adb0 ? adb18 ? address bus output (fig. 6 ? 29) these 19 lines provide the ccu address bus output to access external memory. pin 2, 16, vsupadb* ? supply voltage, address bus driver this pin is used as supply for the address bus driver. pin 3, 17, gndadb * ? ground, address bus driver this is the ground reference for the address bus driver. pins 23 ? 26, 29 ? 32, db0 ? db7 ? data bus input/out- put (fig. 6 ? 30) these 8 lines provide the bidirectional ccu data bus to access external memory. pin 27, vsupdb* ? supply voltage, data bus driver this pin is used as supply for the ccu data bus driver. pin 28, gnddb * ? ground, data bus driver this is the ground reference for the ccu data bus driver. pin 55, disintrom ? disable internal rom input (fig. 6 ? 5) a high level at this pin disables the internal ccu pro- gram memory during reset. in this case the ccu loads the control word from external address location h ? fff9. pin 56 ? 59, p27 ? p24 ? i/o port (fig. 6 ? 27) these pins provide ccu controlled i/o ports. pin 60, vsupp2* ? supply voltage, port 2 driver this pin is used as supply for the i/o port 2 driver. pin 61, gndp2 * ? ground, port 2 driver this is the ground reference for the i/o port 2 driver. pins 66 ? 74, vbclk, vb0 ? vb7 ? digital video bus input (fig. 6 ? 31) in future versions of vct 38xxa/b these pins will pro- vide the itu ? r 656 video interface. as long as the itu-r 656 video interface is not available, these pins have to be connected to gnd d . pin 75, clk20 ? main clock output (fig. 6 ? 8) this is the 20.25 mhz main clock output. pin 79 ? 82, 85 ? 88, p37 ? p30 ? i/o port (fig. 6 ? 27) these pins provide ccu controlled i/o ports. pin 83, vsupp3* ? supply voltage, port 3driver this pin is used as supply for the i/o port 3 driver. pin 84, gndp3 * ? ground, port 3driver this is the ground reference for the i/o port 3 driver. pin 124, we1q ? write enable output 1 (fig. 6 ? 29) this pin controls the direction of data exchange between the ccu and the external program memory device. pin 125, we2q ? write enable output 2 (fig. 6 ? 29) this pin controls the direction of data exchange between the ccu and external the teletext page mem- ory device. pin 126, oe1q ? output enable output 1 (fig. 6 ? 29) this pin is used to enable the output driver of the external program memory device for read access. pin 127, oe2q ? output enable output 1 (fig. 6 ? 29) this pin is used to enable the output driver of the external teletext page memory device for read access. * application note: all ground pins should be connected to one low-resis- tive ground plane. all supply pins should be connected separately with short and low-resistive lines to the power supply. decoupling capacitors from vsup xx to gnd xx are recommended as closely as possible to these pins. decoupling of vsup d and gnd d is most important. we recommend using more than one capacitor. by choosing different values, the frequency range of active decoupling can be extended.
preliminary data sheet vct 38xxa/b micronas 155 6.5. pin configuration fig. 6 ? 3: psdip64 package 1 p17 2 p16 3 vsupp1 4 gndp1 5 p15 6 p14 7 p13 8 p12 9 p11 10 vin5/p10 11 vout 12 vrt 13 sgnd 14 gndaf 15 vsupaf 16 cbin p20 64 p21 63 p22 62 p23 61 sda 60 scl 59 resq 58 xtal2 57 xtal1 56 gnds 55 vsups 54 aout1 53 aout2 52 ain1 51 ain2 50 ain3 49 17 cin1 18 cin2/crin 19 vin1 20 vin2 21 vin3 22 vin4 23 test 24 hout 25 vsupd 26 gndd xref 48 vrd 47 gndab 46 vsupab 45 bout 44 gout 43 rout 42 svmout 41 rsw2 40 rsw1 39 fblin rin gin bin vprot safety 38 37 36 35 34 33 27 28 29 30 31 32 gndm sense ew vert vertq hflb vct 38xxa/b
vct 38xxa/b preliminary data sheet 156 micronas fig. 6 ? 4: pmqfp128 package 48 113 ain2 114 ain1 115 aout2 116 aout1 117 resq 118 scl 119 sda 120 xtal1 121 xtal2 122 vsups 123 gnds 124 we1q 125 we2q 126 oe1q 127 oe2q 128 adb18 cbin vsupaf 47 gndaf 46 sgnd 45 vrt 44 vout 43 p10/vin5 42 p11 41 p12 40 p13 39 gndp1 38 vsupp1 37 p14 36 p15 35 p16 34 p17 33 vsupadb gndadb adb16 adb15 adb14 adb13 adb12 adb11 adb10 adb17 adb9 adb8 1 2 3 4 5 6 7 8 9 1011 12131415161718192021222324 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 25 26 27 28 29 30 31 32 adb7 adb6 adb5 vsupadb adb1 adb0 db0 db1 db2 db3 vsupdb gnddb db4 db5 db6 db7 adb2 adb3 adb4 gndadb 72 71 70 69 68 67 66 65 49 cin1 50 cin2/crin 51 vin1 52 vin2 53 vin3 54 vin4 55 disintrom 56 p27 57 p26 58 p25 59 p24 60 vsupp2 61 gndp2 62 p23 63 p22 64 p21 97 vertq 98 vert 99 ew 100 sense 101 gndm 102 rsw1 103 rsw2 104 svmout 105 rout 106 gout 107 bout 108 vsupab 109 gndab 110 vrd 111 xref 112 ain3 safety vprot bin gin rin fblin test p30 p31 hflb p32 p33 gndp3 vsupp3 p34 p35 hout clk20 vb0 vb1 vb2 vb3 vb4 vb5 vb6 vb7 vbclk p20 vsupd gndd p37 p36 vct 38xxa/b
preliminary data sheet vct 38xxa/b micronas 157 6.6. pin circuits fig. 6 ? 5: input pins test, disintrom fig. 6 ? 6: input/output pins resq, sda, scl fig. 6 ? 7: input/output pins xtal1, xtal2 fig. 6 ? 8: output pin clk20 fig. 6 ? 9: input pins vin1 ? vin5 fig. 6 ? 10: input pins cin1, cin2 fig. 6 ? 11: input pins crin, cbin fig. 6 ? 12: output pin vout fig. 6 ? 13: supply pins vrt, sgnd vsup s gnd s n gnd s vsup s gnd s vsup s p n p n f xtal 0.5m xtal2 xtal1 n p gnd d p n vsup d gnd af vsup af to adc gnd af vsup af to adc gnd af vsup af to adc vsup af gnd af p n vinx vref ? + vsup af p sgnd vrt v ref adc reference ? + =
vct 38xxa/b preliminary data sheet 158 micronas fig. 6 ? 14: input pins rin, gin, bin fig. 6 ? 15: output pins rout, gout, bout, svmout fig. 6 ? 16: output pin hout fig. 6 ? 17: input pins safety, vprot, hflb fig. 6 ? 18: input pin fblin fig. 6 ? 19: output pin intlc fig. 6 ? 20: output pins vert, vertq fig. 6 ? 21: output pin ew fig. 6 ? 22: output pins rsw1, rsw2 gnd ab n clamping pp vsup ab gnd ab bias n n gnd d n v ref vsup ab gnd ab v ref vsup ab gnd ab gnd ab p n vsup ab p p vsup ab gnd ab n flyback vert vertq p vsup ab gnd ab n vewxr pp gnd ab n
preliminary data sheet vct 38xxa/b micronas 159 fig. 6 ? 23: input pin sense fig. 6 ? 24: supply pins xref, vrd fig. 6 ? 25: input pins ain1-3 fig. 6 ? 26: output pins aout1, aout2 fig. 6 ? 27: input/output pins p10-p17, p20-p27, p30- p37 fig. 6 ? 28: input pins p42-p46 fig. 6 ? 29: output pins adb0-adb18, oe1 , oe2 , we1 , we2 fig. 6 ? 30: input/output pins db0-db7 fig. 6 ? 31: input pins vb0-vb7, vbclk n p + - ref. current vsup ab gnd ab vrd xref int. ref. voltage 2.5 v 40 k gnd ab 80 k 2.5 v gnd ab gnd px p n vsup px vsup s to adc gnd ab p n vsup ab p n vsup s p n gnd adb vsup adb vsup db gnd db p n vsup s vsup d gnd d
vct 38xxa/b preliminary data sheet 160 micronas 6.7. electrical characteristics 6.7.1. absolute maximum ratings 1) refer to pin circuits (chapter 6.6. on page 157) stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 6.7.2. recommended operating conditions 6.7.2.1. general recommendations symbol parameter pin name min. max. unit t a ambient operating temperature ? 65 c t s storage temperature ? 40 125 c p tot total power dissipation ? 1400 mw vsup x supply voltage vsup x ? 0.3 6 v v i input voltage, all inputs ? 0.3 vsup x +0.3 1) v v o output voltage, all outputs ? 0.3 vsup x +0.3 1) v v io input/output voltage, all open drain out- puts ? 0.3 6 v symbol parameter pin name min. typ. max. unit t a ambient operating temperature 0 ? 65 c t c case operating temperature (psdip64) 0 ? 105 c t c case operating temperature (pmqfp128) 0 ? 105 c f xtal clock frequency xtal1/2 ? 20.25 ? mhz vsup a analog supply voltage vsup af vsup ab 4.75 5.0 5.25 v vsup d digital supply voltage vsup s vsup d vsup vdp vsup tpu vsup ccu 3.15 3.3 3.45 v vsup p port supply voltage vsup px vsup db vsup adb 3.15 3.3/5.0 5.25 v vsup off standby supply voltage vsup af vsup ab vsup d 0 ? 0.5 v vsup ? difference between standby and emulator supply voltage vsup s vsup vdp vsup tpu vsup ccu 0 ? 0.3 v
preliminary data sheet vct 38xxa/b micronas 161 6.7.2.2. analog input and output recommendations symbol parameter pin name min. typ. max. unit audio c ain input coupling capacitor audio inputs ain1 ? 3 ? 330 ? nf v ain audio input level ?? 1.0 v rms r laout audio output load resistance aout1 ? 210 ?? k ? c laout audio output load capacitance ?? 1.0 nf r saout audio output serial resistance ? 680 ?? video v vin video input level vin1 ? 5, cin1 ? 2 0.5 1.0 3.5 v v cin chroma input level crin, cbin ? 700 ? mv c vin input coupling capacitor video inputs vin1 ? 5 ? 680 ? nf c cin input coupling capacitor chroma inputs cin1 ? 2 ? 1 ? nf c ccin input coupling capacitor component inputs crin, cbin ? 220 ? nf rgb r xref rgb ? dac current defining resistor xref 9.5 10 10.5 k ? c rgbin rgb input coupling capacitor rin gin bin ? 15 ? nf deflection r load deflection load resistance ew, vert, vertq ? 6.8 ? k ? c load deflection load capacitance ? 68 ? nf
vct 38xxa/b preliminary data sheet 162 micronas 6.7.2.3. recommended crystal characteristics symbol parameter min. typ. max. unit t a operating ambient temperature 0 ? 65 c f p parallel resonance frequency with load capacitance c l = 13 pf ? 20.250000 ? mhz ? f p /f p accuracy of adjustment ?? 20 ppm ? f p /f p frequency temperature drift ?? 30 ppm r r series resistance ?? 25 ? c 0 shunt capacitance 3 ? 7pf c 1 motional capacitance 20 ? 30 ff load capacitance recommendation c lext external load capacitance 1) from pins to ground (pin names: xtal1 xtal2) ? 3.3 ? pf dco characteristics 2,3) c icloadmin effective load capacitance @ min. dco ? position, code 0, package: 64psdip 34.35.5pf c icloadrng effective load capacitance range, dco codes from 0..255 11 12.7 15 pf 1) remarks on defining the external load capacitance: external capacitors at each crystal pin to ground are required. they are necessary to tune the effective load capacitance of th e pcbs to the required load capacitance c l of the crystal. the higher the capacitors, the lower the clock frequency results. the nominal free running fre- quency should match f p mhz. due to different layouts of customer pcbs the matching capacitor size should be determined in the application. the suggested value is a figure based on experience with various pcb layouts. tuning condition: code dvco register= ? 720 2) remarks on pulling range of dco: the pulling range of the dco is a function of the used crystal and effective load capacitance of the ic (c icload +c loadboard ). the resulting fre- quency f l with an effective load capacitance of c leff = c icload + c loadboard is: 1 + 0.5 * [ c 1 / (c 0 + c leff ) ] f l = f p * _______________________ 1 + 0.5 * [ c 1 / (c 0 + c l ) ] 3) remarks on dco codes the dco hardware register has 8 bits, the fp control register uses a range of ? 2048...2047
preliminary data sheet vct 38xxa/b micronas 163 6.7.3. characteristics if not otherwise designated under test conditions, all characteristics are specified for recommended operating condi- tions (see section 6.7.2. on page 160). 6.7.3.1. general characteristics 6.7.3.2. test input symbol parameter pin name min. typ. max. unit test conditions p tot total power dissipation ? 850 1350 mw p stdby standby power dissipation vsup s ? tbd tbd mw vsup d = vsup p = vsup af = vsup ab = vsup db = vsup adb = 0v sr0 = sr1 = sr2 = 0 i vsups current consumption standby mode ? tbd tbd ma i vsups current consumption standby supply ? 15 23 ma normal operation i vsupd current consumption digital cir- cuitry vsup d ? 55 83 ma i vsupp current consumption port cir- cuitry vsup p ?? ? ma depends on port load i vsupaf current consumption analog front-end vsup af ? 48 72 ma i vsupab current consumption analog back-end vsup ab ? 50 100 ma depends on contrast and brightness settings i l input and output leakage cur- rent all i/o pins ? 1 ? 1 a symbol parameter pin name min. typ. max. unit test conditions v il input low voltage test ?? 0.8 v v ih input high voltage 2.0 ?? v
vct 38xxa/b preliminary data sheet 164 micronas 6.7.3.3. reset input/output 6.7.3.4. i 2 c bus interface symbol parameter pin name min. typ. max. unit test conditions vbg internal reference voltage resq 1.125 1.25 1.375 v tbg internal voltage reference setup time after power-up ? 30 60 us vrefr reset comparator reference voltage ? 1*vbg ? v rvlh ? rvhl reset comparator hysteresis, symmetrical to vrefr 0.25 0.313 0.375 v vrefa alarm comparator reference voltage ? 2*vbg ? v avlh ? avhl alarm comparator hysteresis, symmetrical to vrefa 60 90 120 mv tcdel reset, alarm comparator delay time ?? 100 ns overdrive=50mv v ol output low voltage ?? 0.4 0.6 v v i l = 3 ma i l = 6 ma vrefpor power on reset comparator reference voltage vsup s ? 2*vbg ? v symbol parameter pin name min. typ. max. unit test conditions v il input low voltage sda, scl ?? 0.3* vsup s v v ih input high voltage 0.6* vsup s ?? v v ol output low voltage ?? 0.4 0.6 v v i l = 3 ma i l = 6 ma c i input capacitance ?? 5pf t f signal fall time ?? 300 ns c l = 400 pf t r signal rise time ?? 300 ns c l = 400 pf f scl clock frequency scl 0 ? 400 khz t low low period of scl 1.3 ?? s t high high period of scl 0.6 ?? s t su data data set up time to scl high sda 100 ?? ns t hd data data hold time to scl low 0 ? 0.9 s
preliminary data sheet vct 38xxa/b micronas 165 6.7.3.5. 20-mhz clock output 6.7.3.6. analog video output 6.7.3.7. a/d converter reference symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage clk20 ?? 0.4 v i ol = 13ma @ strength 000 i ol = 1.7ma @ strength 111 v oh output high voltage vsup d ? 0.4 ? vsup d vi oh = 12ma @ strength 000 i oh = 1.6ma @ strength 111 symbol parameter pin name min. typ. max. unit test conditions v out output voltage vout 1.7 2.0 2.3 v pp v vin = 1 v pp , agc = 0 db agc vout agc step width, vout 1.333 db 3 bit resolution = 7 steps 3 msb ? s of main agc dnl agc agc differential non-linearity 0.5 lsb v outdc dc-level 1 v clamped to back porch bw v out bandwidth 6 10 ? mhz input: ? 2 dbr of main adc range, c l 10 pf thd v out total harmonic distortion -45 -40 db input: ? 2 dbr of main adc range, c l 10 pf 1 mhz, 5 harmonics, y/c adder off tbd tbd db y/c adder on xtalk lc luma/chroma crosstalk tbd tbd db agc = 0db y = 1mhz 1vpp c = 4.43mhz 300mvpp y/c adder off c lvout load capacitance ?? 10 pf i lvout output current ?? 0.1 ma symbol parameter pin name min. typ. max. unit test conditions v vrt reference voltage top vrt 2.5 2.6 2.8 v 10 f/10 nf, 1 g ? probe v vrtn reference voltage top noise ?? 100 mv pp
vct 38xxa/b preliminary data sheet 166 micronas 6.7.3.8. analog video front-end and a/d converters symbol parameter pin name min. typ. max. unit test conditions luma ? path (composite) r vin input resistance vin1 ? 51 ?? m ? code clamp ? dac=0 c vin input capacitance ? 5 ? pf v vin full scale input voltage 1.8 2.0 2.2 v pp min. agc gain v vin full scale input voltage 0.5 0.6 0.7 v pp max. agc gain agc agc step width ? 0.166 ? db 6-bit resolution= 64 steps f sig =1mhz, ? 2 dbr of max. agc ? gain dnl agc agc differential non-linearity ?? 0.5 lsb v vincl input clamping level, cvbs ? 1.0 ? v binary level = 64 lsb min. agc gain q cl clamping dac resolution ? 16 ? 15 steps 5 bit ? i ? dac, bipolar v vin =1.5 v i cl ? lsb input clamping current per step 0.7 1.0 1.3 a dnl icl clamping dac differential non- linearity ?? 0.5 lsb chroma ? path (composite) r cin input resistance svhs chroma cin1 cin2 1.4 2.0 2.6 k ? v cin full scale input voltage, chroma 1.08 1.2 1.32 v pp v cindc input bias level, svhs chroma ? 1.5 ? v binary code for open chroma input ? 128 ?? chroma ? path (component) r cin input resistance crin cbin 1 ?? m ? code clamp ? dac=0 c cin input capacitance ?? 4.5 pf v cin full scale input voltage 0.76 0,84 0.92 v pp minimal range v cin full scale input voltage 1.08 1.2 1.32 v pp extended range v cincl input clamping level c r , c b ? 1.5 ? v binary level = 128 lsb q cl clamping dac resolution ? 32 ? 31 steps 6 bit ? i ? dac, bipolar v vin =1.5 v i cl ? lsb input clamping current per step 0.59 0.85 1.11 a dnl icl clamping dac differential non- linearity ?? 0.5 lsb
preliminary data sheet vct 38xxa/b micronas 167 dynamic characteristics for all video-paths (luma + chroma) bw bandwidth vin1 ? 5 cin1 ? 2 cbin 810 ? mhz ? 2 dbr input signal level xtalk crosstalk, any two video inputs ?? 56 ? db 1 mhz, ? 2 dbr signal level thd total harmonic distortion ? 50 ? db 1 mhz, 5 harmonics, ? 2 dbr signal level sinad signal-to-noise and distortion ratio ? 45 ? db 1 mhz, all outputs, ? 2 dbr signal level inl integral non-linearity ?? 1 lsb code density, dc-ramp dnl differential non-linearity ?? 0.8 lsb dg differential gain ?? 3% ? 12 dbr, 4.4 mhz signal on dc-ramp dp differential phase ?? 1.5 deg symbol parameter pin name min. typ. max. unit test conditions
vct 38xxa/b preliminary data sheet 168 micronas 6.7.3.9. analog rgb and fb inputs symbol parameter pin name min. typ. max. unit test conditions rgb input characteristics v rgbin external rgb inputs voltage range rin gin bin ? 0.3 ? 1.1 v v rgbin nominal rgb input voltage peak-to-peak 0.5 0.7 1.0 v pp scart spec: 0.7v 3db v rgbin rgb inputs voltage for maxi- mum output current ? 0.44 ? v contrast setting: 511 ? 0.7 ? v contrast setting: 323 ? 1.1 ? v contrast setting: 204 t clp clamp pulse width 1.6 ?? s c in input capacitance ?? 13 pf i il input leakage current ? 0.5 ? 0.5 a clamping off, v in = ? 0.3...3 v v clip rgb input voltage for clipping current ? 2 ? v v clamp clamp level at input 40 60 80 mv clamping on v inoff offset level at input ? 10 ? 10 mv extrapolated from v in = 100 and 200 mv v inoff offset level match at input ? 10 ? 10 mv extrapolated from v in = 100 and 200 mv r clamp clamping-on-resistance 20 40 80 ? i clamp =10ma fast blank input characteristics v fbloff fast blanking low level fblin ?? 0.5 v v fblon fast blanking high level 0.9 ?? v v fbltrig fast blanking trigger level ? 0.7 ? v t pid delay fast blanking to rgb out from midst of fblin ? transition to 90% of rgb out - transition ? 8 15 ns internal rgb = 3.75 ma full scale int. brightness = 0 external brightness = 1.5 ma (full scale) rgbin = 0 v fbloff = 0.4 v v fblon = 1.0 v rise and fall time = 2 ns difference of internal delay to external rgbin delay ? 5 ? +5 ns switch-over-glitch ? 0.5 ? pas switch from 3.75 ma (int) to 1.5 ma (ext)
preliminary data sheet vct 38xxa/b micronas 169 6.7.3.10. horizontal flyback input 6.7.3.11. horizontal drive output 6.7.3.12. vertical safety input 6.7.3.13. vertical protection input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage hflb ?? 1.8 v v ih input high voltage 2.6 ?? v v ihst input hysteresis 0.1 ?? v psrr hf power supply rejection ratio of trigger level 0 ?? db f = 20 mhz psrr mf power supply rejection ratio of trigger level ? 20 ? ? db f < 15 khz psrr lf power supply rejection ratio of trigger level ? 40 ?? db f < 100 hz symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage hout ?? 0.4 v i ol = 10 ma v oh output high voltage (open drain stage) ?? 5 v external pull-up resistor t of output fall time ? 5-nsc load = 30pf i ol = 60 ma i ol output low current 30 60 80 ma symbol parameter pin name min. typ. max. unit test conditions v ila input low voltage a safety ?? 1.8 v v iha input high voltage a 2.6 ?? v v ilb input low voltage b ?? 3.0 v v ihb input high voltage b 3.8 ?? v v ihst input hysteresis a and b 0.1 ?? v t pid internal delay ?? 100 ns symbol parameter pin name min. typ. max. unit test conditions v il input low voltage vprot ?? 1.8 v v ih input high voltage 2.6 ?? v v ihst input hysteresis 0.1 ?? v
vct 38xxa/b preliminary data sheet 170 micronas 6.7.3.14. vertical and east / west d/a converter output 6.7.3.15. interlace output 6.7.3.16. sense a/d converter input 6.7.3.17. range switch output symbol parameter pin name min. typ. max. unit test conditions v omin minimum output voltage ew vert vertq ? 0 ? vr load = 6.8 k ? r xref = 10 k ? v omax maximum output voltage 2.82 3 3.2 v r load = 6.8 k ? r xref = 10 k ? i dacn full scale dac output current 415 440 465 ar xref = 10 k ? psrr power supply rejection ratio ? 20 ? db symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage intlc ? 0.2 0.4 v i ol = 1.6 ma v oh output high voltage vsup a b ? 0.4 vsup a b ? 0.2 ? v ? i ol = 1.6ma symbol parameter pin name min. typ. max. unit test conditions v i input voltage range sense 0 ? vsup a b v v i255 input voltage for code 255 1.4 1.54 1.7 v read cutoff blue register c 0 digital output for zero input ?? 16 lsb offset check, read cutoff blue register r i input impedance 1 ?? m ? symbol parameter pin name min. typ. max. unit test conditions r on output on resistance rsw1 rsw2 ?12 25 ? i ol = 10 ma i max maximum current ?? 15 ma i leak leakage current ?? 600 na rsw high impedance c in input capacitance ?? 5pf
preliminary data sheet vct 38xxa/b micronas 171 6.7.3.18. d/a converter reference 6.7.3.19. analog rgb outputs, d/a converters symbol parameter pin name min. typ. max. unit test conditions v dacref dac-ref. voltage vrd 2.38 2.50 2.67 v v dacr dac-ref. output resistance 18 25 32 k ? v xref dac-ref. voltage bias current generation xref 2.38 2.5 2.67 v r xref = 10 k ? symbol parameter pin name min. typ. max. unit test conditions internal rgb signal d/a converter characteristics resolution rout gout bout ? 10 ? bit i out full scale output current 3.6 3.75 3.9 ma r ref = 10 k ? i out differential nonlinearity ?? 0.5 lsb i out integral nonlinearity ?? 1lsb i out glitch pulse charge ? 0.5 ? pas ramp signal, 25 ? output ter- mination i out rise and fall time ? 3 ? ns 10% to 90%, 90% to 10% i out intermodulation ??? 50 db 2/2.5mhz full scale i out signal to noise +50 ?? db signal: 1mhz full scale band- width: 10mhz i out matching r-g, r-b, g-b ? 2 ? 2% r/b/g crosstalk one channel talks two channels talk ??? 46 db passive channel: i out =1.88 ma crosstalk-signal: 1.25 mhz, 3.75 ma pp rgb input crosstalk from exter- nal rgb one channel talks two channels talk three channels talk ? ? ? ? ? ? ? 50 ? 50 ? 50 db db db internal rgb brightness d/a converter characteristics resolution rout gout bout ? 9 ? bit i br full scale output current rela- tive 39.2 40 40.8 % ref to max. digital rgb i br full scale output current abso- lute ? 1.5 ? ma i br differential nonlinearity ?? 1lsb i br integral nonlinearity ?? 2lsb i br match r-g, r-b, g-b ? 2 ? 2% i br match to digital rgb r-r, g-g, b-b ? 2 ? 2%
vct 38xxa/b preliminary data sheet 172 micronas external rgb voltage/current converter characteristics resolution rout gout bout ? 9 ? bit i exout full scale output current rela- tive 96 100 104 % ref. to max. digital rgb v in = 0.7 v pp , contrast = 323 full scale output current absolute ? 3.75 ? ma same as digital rgb cr contrast adjust range ? 16:511 ? gain match r-g, r-b, g-b ? 3 ? 3 % measured at rgb outputs v in = 0.7 v, contrast = 323 gain match to rgb-dacs r-r, g-g, b-b ? 3 ? 3 % measured at rgb outputs v in = 0.7 v, contrast = 323 r/b/g input crosstalk one channel talks two channels talk ??? 46 db passive channel: v in = 0.7v, contrast = 323 crosstalk signal: 1.25 mhz, 3.75 ma pp rgb input crosstalk from internal rgb one channel talks two channels talk tree channels talk ??? 50 db rgb input noise and distortion ??? 50 db v in =0.7 v pp at 1 mhz contrast = 323 bandwidth: 10 mhz rgb input bandwidth -3db 15 ? mhz v in = 0.7 v pp , contrast =323 rgb input thd ? ? ? 50 ? 40 ? ? db db input signal 1 mhz input signal 6 mhz v in = 0.7 v pp contrast =323 differential nonlinearity of contrast adjust ?? 1lsbv in = 0.44v integral nonlinearity of contrast adjust ?? 2lsb v rgbo r,g,b output voltage ? 1.0 ? 0.3 v referred to v supo r,g,b output load resistance ?? 100 ? ref. to v supo v outc rgb output compliance ? 1.5 ? 1.3 ? 1.2 v ref. to v supo sum of max. current of rgb-dacs and max. current of int. bright- ness dacs is 2% degraded symbol parameter pin name min. typ. max. unit test conditions
preliminary data sheet vct 38xxa/b micronas 173 external rgb brightness d/a converter characteristics resolution rout gout bout ? 9 ? bit i exbr full scale output current rela- tive 39.2 40 40.8 % ref to max. digital rgb full scale output current abso- lute ? 1.5 ? ma differential nonlinearity ?? 1lsb integral nonlinearity ?? 2lsb matching r-g, r-b, g-b ? 2 ? 2% matching to digital rgb r-r, g- g, b-b ? 2 ? 2% rgb output cutoff d/a converter characteristics resolution rout gout bout ? 9 ? bit i cut full scale output current rela- tive 58.8 60 61.2 % ref to max. digital rgb full scale output current abso- lute ? 2.25 ? ma differential nonlinearity ?? 1lsb integral nonlinearity ?? 2lsb matching to digital rgb r-r, g- g, b-b ? 2 ? 2% rgb output ultrablack d/a converter characteristics resolution rout gout bout ? 1 ? bit i ub full scale output current relative 19.6 20 20.4 % ref to max. digital rgb full scale output current absolute ? 0.75 ? ma match to digital rgb r ? r, g ? g, b ? b ? 2 ? 2% symbol parameter pin name min. typ. max. unit test conditions
vct 38xxa/b preliminary data sheet 174 micronas 6.7.3.20. scan velocity modulation output 6.7.3.21. analog audio inputs and outputs symbol parameter pin name min. typ. max. unit test conditions resolution svmout ? 8 ? bit i out full scale output current 1.55 1.875 2.25 ma i out differential nonlinearity ?? 0.5 lsb i out integral nonlinearity ?? 1lsb i out glitch pulse charge ? 0.5 ? pas ramp, output line is termi- nated on both ends with 50 ? i out rise and fall time ? 3 ? ns 10% to 90%, 90% to 10% symbol parameter pin name min. typ. max. unit test conditions r ain audio input resistance ain1-3 aout1-2 25 40 58 k ? f signal = 1 khz, i = 0.05 ma dv aout deviation of dc-level at audio output from gnd ab voltage ? 20 ? +20 mv a audio gain from audio input to audio output ? 1.0 0.0 +0.5 db f signal = 1 khz avol = 0db f raudio frequency response from audio input to audio output bandwidth: 50 hz to 15000 hz ? 0.5 0.0 +0.5 db with ??? . to 1 khz psrr power supply rejection ratio for audio output tbd 50 ? db 1 khz sine at 100 mv rms tbd 20 ? db 100 khz sine at 100 mv rms v noise noise output voltage ? tbd 20 vr gen = 1k ? , equally weighted 50 hz...15 khz v mute mute output voltage ? tbd 2 vavol = mute, equally weighted 50 hz...15 khz thd total harmonic distortion from audio input to audio output ?? 0.1 % input level = 0.7 v rms , f sig = 1 khz, equally weighted 50 hz...15 khz xtalk crosstalk attenuation between audio input and audio output 70 ?? db input level = 0.7 v rms , f sig = 1 khz, equally weighted 50 hz...15 khz, unused analog inputs connected to ground by z < 1 k ?
preliminary data sheet vct 38xxa/b micronas 175 6.7.3.22. adc input port 6.7.3.23. universal port & memory interface symbol parameter pin name min. typ. max. unit test conditions vref adc comparator reference voltage px.y ? 0.5* vsup s ? v vlh ? vhl adc comparator hysteresis, symmetrical to vref 0.1 0.17 0.24 v tcdel adc comparator delay time ?? 100 ns overdrive=50mv lsb lsb value ? vsup s /1024 ? v r conversion range gnd s ? vsup s v a conversion result ? int (vin/ lsb) ? hex gnd s =vsup s tc conversion time ? 4 ? s ts sample time ? 2 ? s dnl differential non-linearity ? 3 ? 3lsb inl integral non-linearity ? 4 ? 4lsb offset offset error ? 16 ? 16 lsb ci input capacitance during sam- pling period ? 15 ? pf ri serial input resistance during sampling period ? 5 ? k ? symbol parameter pin name min. typ. max. unit test conditions vol output low voltage p1x p2x p3x adb[18-0] db[7:0] oe1q oe2q we1q we2q ?? 0.4 1.0 vio=3ma io=10ma voh output high voltage vsup p ? 0.4 vsup p ? 1.5 ?? vio= ? 3ma io= ? 10ma v il input low voltage p1x p2x p3x p42 ? p46 db[7:0] ?? 0.8 v v ih input high voltage 2.0 ?? v ii input leakage current ? 1.0 ? 1.0 a 0 vct 38xxa/b preliminary data sheet 176 micronas 6.7.3.24. memory interface fig. 6 ? 32: memory port timing symbol parameter pin name min. typ. max. unit test conditions t cyc ph2 cycle time ? 98.77 ? ns t ads address setup time adb[18 ? 0] ? 15 + 0.5 20 30 19 + 0.7 26 40 ns ns/pf ns ns c adb = 0 pf c adb = 10 pf c adb = 30 pf t adh address hold time ? 810nsc adb = 10 pf t dws data write setup time db[7:0] ? 9 + 0.5 14 24 14 + 0.7 21 35 ns ns/ pf ns ns c db = 0 pf c db = 10 pf c db = 30 pf t dwh data write hold time ? 68nsc db = 0 pf t drs data read setup time 12 ?? ns t drh data read hold time 6 ?? ns t ens enable setup time oe1q oe2q we1q we2q ? 610nsc oeq,weq = 0 pf t enh enable hold time ? 69nsc oeq,weq = 0 pf ph2 db[7:0] db[7:0] write data read data adb[18:0] t adh t ads t acc t drs t drh t dwh t dws t enh t ens weq, oeq t cyc
preliminary data sheet vct 38xxa/b micronas 177 7. application fig. 7 ? 1: vct 38xxa/b application circuit, part 1/3
vct 38xxa/b preliminary data sheet 178 micronas fig. 7 ? 2: vct 38xxa/b application circuit, part 2/3
preliminary data sheet vct 38xxa/b micronas 179 fig. 7 ? 3: vct 38xxa/b application circuit, part 3/3
vct 38xxa/b preliminary data sheet 180 micronas 8. glossary of abbreviations ait additional information table btt basic top table bttl basic top table list ccu central control unit clut color look up table cpu central processing unit cri clock running-in dma direct memory access dram dynamic random access memory flof full level one features frc framing code mpt multipage table mpet multipage extension table nmi non maskable interrupt osd on screen display pdc programme delivery control plt page linking table ram random access memory rom read only memory sram static random access memory top table of pages tpu teletext processing unit ttx teletext vbi vertical blanking interval vps video-programm-system wss wide screen signalling wst world system teletext 9. references 1. preliminary data sheet: ? vdp 31xxb ? , sept. 25, 1998 6251-437-2pd 2. preliminary data sheet: ? tpu 3035, tpu 3040, tpu 3050 ? , feb. 23, 1999 6251-349-6pd 3. preliminary data sheet: ? w65c02 ? , oct. 2, 1991 6251-364-1pd 4. ? enhanced teletext specification ? . european telecommunication standard ets 300 706. etsi, may1997. 5. ? television systems; 625-line television wide screen signalling (wss) ? . european telecommuni- cation standard ets 300 294. etsi, may1996. 6. ? television systems; specification of the domestic video programme delivery control system (pdc) ? . european telecommunication standard ets 300 231. etsi, august1996. 7. ? electronic programme guide (epg) ? . european telecommunication standard ets 300 707. etsi, may1997.
preliminary data sheet vct 38xxa/b micronas 181
all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. vct 38xxa/b preliminary data sheet 182 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-518-1pd 10. data sheet history 1. preliminary data sheet: ? vct 38xxa/b video/con- troller/teletext ic family ? , edition jan. 8, 2002, 6251-518-1pd. first release of the preliminary data sheet.

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